wkong_zhu
Full Member level 3
- Joined
- Nov 13, 2004
- Messages
- 174
- Helped
- 4
- Reputation
- 8
- Reaction score
- 0
- Trophy points
- 1,296
- Activity points
- 1,293
propagate_constraints
I use bottom-up synthesis method, I set timing constraints on submoduleA, and compile it, then set_dont_touch it, After that, I read the top module file, which instantiated the submoduleA, but I find that, the top module has no timing constraints now, I have to re define the timing constraints for the top module.
The top module timing constraints is almost the same the submoduleA, the clocks are defined in the submoduleA's internal module Pins. So the re-definition of timing constraints of top module seems to be superfluous and tidious.
How can DC directly transfer submodule timing constraints to uplevel module??
I use bottom-up synthesis method, I set timing constraints on submoduleA, and compile it, then set_dont_touch it, After that, I read the top module file, which instantiated the submoduleA, but I find that, the top module has no timing constraints now, I have to re define the timing constraints for the top module.
The top module timing constraints is almost the same the submoduleA, the clocks are defined in the submoduleA's internal module Pins. So the re-definition of timing constraints of top module seems to be superfluous and tidious.
How can DC directly transfer submodule timing constraints to uplevel module??
