KHDAK
Junior Member level 1
Hi,
I am trying to synthesize a FPGA based design with Cadence RTL compiler to find out the performance difference with ASIC implementation. The elaboration phase works fine but when I try to synthesize "synthesize -to_mapped" I got an error message saying "unable to map design without a suitable latch". I am using COREX9GPHS_Nom.lib library for 130nm process. Can someone please explain what should I need to do.
Thanks
I am trying to synthesize a FPGA based design with Cadence RTL compiler to find out the performance difference with ASIC implementation. The elaboration phase works fine but when I try to synthesize "synthesize -to_mapped" I got an error message saying "unable to map design without a suitable latch". I am using COREX9GPHS_Nom.lib library for 130nm process. Can someone please explain what should I need to do.
Thanks