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[SOLVED] doubts regarding RTL to GDS flow

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yuvraj7792

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I am doing RTL to GDSII of a counter. I have written a code for it in VHDL. I am synthesizing it using Design compiler. While synthesizing, it is giving a warning for the unconnected outputs of the flipflops. I have left the Q_n output of some flipflops unconnected.
1.How to deal with such outputs?
2.what to do with such outputs while designing layout?
 

I have given "Logic 1" to the inputs of some flip flops. How to deal with such inputs in layout?
 

Usually, synthesis tool will pick up tiehi cell in your standard cell library to implement logic "1". You don't have to do anything special.
 
in general the logic 1 or 0 should be replaced by tie cell 1 or 0. Some technologies accepte to directly connect to the power net, but some other avoid that to respect the ERC.
 
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