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encounter rtl compiler 9.1 dont touch commands

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gourang

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i want to synthesize a design consisting of 6 cascaded inverters , when i type the command synthesize -to mapped its eliminating all inverters . please tell me how to avoid this problem. all i want is 6 cascaded inverters synthesized....:p
 

i believe what the tool here is doing is correct. Basically synthesis is not only supposed to map the RTL to technology gates but perform optimization as well.
Further in your case say 2 back to back inverters would give the same logic as output which was at the input stage thus a buffer. The same is what 6 inverters i.e.3 pairs of inverters are leading to in the design and hence being optimized away.

The question that comes to my mind is why do you need 6 inverters back to back.

Anyways after elaboration you can hand map these inverters with technology libcells and put a preserve / set_dont_touch on the same cells. YOu should find them in your final netlist.
 
i am designing an asynchronous processor , so i need delay cells , so i used 6 back to back inverters. :)
i will try what you said and get back to you. :)
 

Check or try and find out if you lib has delay cells. that may help as well.
Anyways try the above - it should work as well.
 
Sir can you please tell how to hand map these inverters???
by which commands to hand map those inverters???
and also how to use preserve command???
my delay cell module name is dealy3e, inside it there are instantiations of inverters i1,i2,i3,i4,i5,i6.,, the inverter module name is inv, can you please tell how to type these commandas , i am always gettin set_attribute failed or wrong object.. :)
 
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will make it simple for you
1. identify the inverter you wish the synthesis tool to use during synthesis from the library
2. Instantiate it in the RTL itself.

Now as part of the regular flow read and elaborate that RTL. Now use "set_attr preserve true [find / -inst <inverternames>] /" thats it and proceed.
Logic is preserved. Now you must be wondering why earlier preserve failed - it failed cause it will only preserve technology cell, until it is not mapped how can you preserve combinational logic.

Hope this helps.
 
Thank you sir it helped me..
I have one more question ,, when i give command synthesize -to_generic it gives a warning combinational loop has been found and its been disabled.. is this error in the design??? Can you tell how to rectify it???
 
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You may want to search this group for more in-depth details on combo loops to understand it further
Ideally the design should not have these - but it is not always avoidable. Basically the tools breaks these combo loops using a buffer and then disable's it timing arc so that it can time the path.

I think you can report them as well "report_cdn_loop_breaker". So during generic map the tool is probably building some timing graph for which it found a loop hence the Warning message.
 

Hello sir , can you tell me how to find worst case delay of combinational logic or critical path delay of combinational logic in encounter RTL compiler. can you tell what commands to be used?????
 

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