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[STA] Output in Setup and Hold Violation

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maulin sheth

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Hello All,

Can anyone guide me, what is the flip flop output when there is a hold violation and what is the output when there is a setup violation?
In both cases the output is same as previous or don't care(0 or 1 whatever we don't know).

Thanks & Regards,
Maulin Sheth
 

Actually, we say that the output will be metastable state.

By if Set up and Hold violations happen , the output will not be same as expected.Eg If you are expecting 1, it will be 0.

There are some cases that due to some noise present, even if set up violations occur the output will be 1, but if again such environment is encountered then the output will be 0. Meaning the output wont be stable.

Hope this Helps!!
 
Thanks.
It's mean that it if any setup/hold violation occur than it does not depend on the previous stored bit?
 

maulin sheth said:
It's mean that it if any setup/hold violation occur than it does not depend on the previous stored bit?
Click to expand...

It does depend upon the previously stored bit.

In case of excess noise(Rare cases), the ouput may be metastable(unexpected).

Here you need to consider the voltage levels also. I mean you are considering 0 and 1, there are chances that ouput may be 0.4 o 0.6.
 

Huh, I am new to this. I never came across slow rise and all..

No much explanation in the link also.

I will try to understand the concept and let you know the status.

Thanks for the link. (New learning)
 

I just give you the overview of this:
Slow to rise and slow to fall is : when we are calculation setup time, thn we considered the maximum propagation delay between two consecutive flops, means maximum propagation delay tends to slow circuit.
fast to rise and fast to fall : when we are calculation hold time, thn we considered the min propagation delay between two consecutive flops, means min propagation delay tends to fast circuit.
Basically these used for the testing purpose means -> if chip is failing on tester, thn how can we know that the chip is failing due to which violation(hold time or setup time)..
 

Hello,

Any update on this?

Whenever we are doing simulation of the scan patterns, if there is hold violation in the scan path, what will be the output of particular violated flop?
 

In case of any violation(setup or hold), the output is known to be metastable(0,1 or undefined). The outcome is not predictable.
 

But I am not able to understand this concept : **broken link removed**
Click to expand...

Are you observing the signals outside of the FPGA?
Sometimes these things are outside the domain of the firmware engineer.
There could be capacitance/inductance on the line etc that effect the behaviour of the signal.

With regards to the insides of an FPGA. Setup time violations in vivado can be related to the timing analysis not identifying that you've used synchronizers etc. It thinks there will be a metastable state.
 

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