Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Folding structure - Mos Transistor

Status
Not open for further replies.
MahmoudHassan

MahmoudHassan

Full Member level 6
Full Member level 6
Joined
Oct 4, 2010
Messages
349
Helped
44
Reputation
90
Reaction score
40
Trophy points
1,328
Activity points
3,919
the attached picture form book Design of Analog Integrated circuit page 35
How can the shown folding structure reduces the gate resistance by factor of 4 .... i think it reduces it by factor 2 only ?

as it is written above this picture " We note that Folding reduces the gate resistance by a factor of four "


 

MahmoudHassan said:
the attached picture form book Design of Analog Integrated circuit page 35
How can the shown folding structure reduces the gate resistance by factor of 4 .... i think it reduces it by factor 2 only ?

as it is written above this picture " We note that Folding reduces the gate resistance by a factor of four "


Click to expand...


1st Case Resistors are in serires so effective R = R+R+R+R = 4R
2nd Case two pair resistors are in series which is in parallel to each-other so effective R = 2R parallel to 2R => 2Rx2R/(2R+2R) = 4RXR/4R =R

so it is reduced by a factor of 4 .
 
but did you say that they are parallel in the second case ?
 

yup...from the figure itself u can identify it, two Rg/2 s are in parallel
 

can you it more clear ....how this two resistors are in parallel ?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top