Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

New to Synthesis,require help

Status
Not open for further replies.
M

Madhusudhan.R

Newbie level 6
Newbie level 6
Joined
Feb 4, 2013
Messages
13
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Location
Bangalore
Activity points
1,357
Hi I'm new to synthesis. I want to learn synthesis from basics.I want to know the topics that are helpful for understanding synthesis better.
 

First thing you need to learn is setup and hold time of FF .
And then you can proceed with the method when you connect the two flops and then add the combo logic b/w the flops what are the delays associated with it.
There are so many online tutorials and synopsys Solvnet user guides , go through it and you should be good to go ..
 
Hi,
The best way is if you have an access to use any synthesis tool, write a simple HDL code and try to synthesis.
Also, keep a good reference book about synthesis with you.

Second is Google :)...then, any issues or doubts, you can post it here.

All the best and enjoy!!
 
Surely , you need to know some basics about the following topics :
Karnaugh maps and realization of digital circuits
constructing truth tables
Combinational and sequential circuits
timing analysis and set-up/hold timing requirements

then have a look on one of the tutorials available online and make sure you get the following :
how to define your technology files needed for synthesis
how to define your design files
how to define your design constraints especially clock period
how to write output files and reports

start with simple examples then complicate it over and over
 
hi,
Thanks.
Why we are doing LEC when we already verifying the function with functional verification?

- - - Updated - - -

hi,
Thanks.
Why we are doing LEC when we already verifying the function with functional verification?
 
  • Like
Reactions: no_mad

    N

    no_mad

    Points: 2
    Helpful Answer Positive Rating
LEC is logical equivalence checking between the RTL and synthesized netlist . Functional verification will be done @ the RTL level and to run all the verification on the gate level netlist it will take more simulator time . Hence LEC is required to compare the logical equivalence between RTL and synthesized netlist ..
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top