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[SOLVED] increasing the linearity range f an OTA

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ashyma

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I am designing an OTA but i am getting a very small linearity range... i need to increase the linearity.. I added passive resistors at the differential pair but i am not getting any improvements... so any ideas???

Thanks
 

there are many ways to increase linearity such as degenerating via resistor or diode, use two differential pair, diffuser, memristor and ...
 

thank you for your help... i am using passive resistors but i am not getting the linearity range that i want.. i recalculate the aspect ratios of the transistors.. but the linearity range is still somehow small
 

Use current mirror based active load for more linearity. or current source for more linearity. There are other technics also to imorove linearity. Please Elaborate more about your requirement and application.
 

check the operating region of your transistors. if you get acceptable linearity of say 1% thd for very small signal amplitudes (10 20 mv ) its because your transistors are operating in weak inversion. if transistors are biased in strong inversion you will be able to get the same thd for much higher signal ampliutudes therfore higher linear range
 

i ahd to remove it ... sorry for that
 
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for M1&M2 are W=8.769n L=90nm
for M3 to M6 are W=5.35u L=180nm
for M7 & M8 are W=2.67u L=180nm
for M9 & M10 are W=8.769nm L=90nm
for Mcascp are W=450n L=1.35u
for Mcascn are W=7.35u L=1.35u
Click to expand...
Width should be in Micrometer. Check the aspect ratio for M10 and M1/M2

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Did you do some mathmatical calculations for your design for 4uA bias current. I doubt that.
 

I have a question. how can we calculate linearity and gain with hspice or similar programs?
 
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varunkant2k ... no i just assumed the Ibias to be 4 u... so do u have any suggestions on how to calculate it... i assumed it and through it i calculay=ted the VSG for the transistors and the aspect ratios

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ahmad1954.. for the linearity range using LTspiece or PSPECE... u need to do dc sweep on the Vin and the plot the Iout and the the same curve the GM by taking d(Iout).... then you take the intersection points and subtract this will be ur linearity range


the gain you just do ac sweep and then plot the dB of Vout .. this will be the gain
 
ashyma said:
no i just assumed the Ibias to be 4 u... so do u have any suggestions on how to calculate it... i assumed it and through it i calculay=ted the VSG for the transistors and the aspect ratios
Click to expand...
Ahyma,
As starter I will suggest you to do calculations and assure transistors current carrying capacity.(in the case of M1/M2 and M9/10). You can start the design with all the transistors width of 10um and Length 500nm. You need to take help of any opamp designing book.
4uA biasing current is not bad. But even 500nA will work but it all depends upon your application.
 
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    ashyma

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ok thanks a lot really appreciate ur help... do you have a book in mind that i can check.. thanks again

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varunkant2k said:
Ahyma,
As starter I will suggest you to do calculations and assure transistors current carrying capacity.(in the case of M1/M2 and M9/10). You can start the design with all the transistors width of 10um and Length 500nm. You need to take help of any opamp designing book.
4uA biasing current is not bad. But even 500nA will work but it all depends upon your application.
Click to expand...

ok really thanks for your reply.. but i have a question what do u mean with "assure transistors current carrying capacity"... how to assure this please .. what teat to i need to do
 

I took all the transistors to be PMOSs
Click to expand...
Seriously, I can't imagine how the low side current mirrors would be implented will "all PMOS". Sounds confused.

and i am getting a very bad curve for the gain as shown below
Click to expand...
Distinct from the linearity point, this looks pretty much like a wrong bias point in AC analysis.

You'll want to show your actual "all PMOS" design and the gain measurement circuit.
 
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