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Dual vs Triple synchronizer on FPGA input

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shaiko

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When is it worthwhile considering Triple DFF synchronizers on FPGA inputs instead of the commonly used Dual DFF ?
 

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    shaiko

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Dual will always give you a 1 or a 0. I only use triple when I need to do edge detection, or data alignment.
 
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    shaiko

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What if the metastability isn't settled for a full clock T and proceeds to the second DFF ?
 

From my understanding, the only problem is the first FF sampling during a transition of the IP, and it can go metastable. The 2nd FF should never sample an edge, so will always flip to 0 or 1, even if the first FF is metastable.
 

TrickyDicky said:
The 2nd FF should never sample an edge, so will always flip to 0 or 1, even if the first FF is metastable.
Click to expand...
You assume that the metastability condition is resolved befor the second clock edge arrives. But what if we are working at a very high frequency and the metastability condition doesn't have enough time to resolve - causing setup time violations?
 
It is not possible to guarantee that metastability problems are avoided.
The MTBF for a circuit can be calculated, and you add synchronizer stages if you want to increase it.

From Altera handbook 12.1, Volume 1, chapter 14:

"Designers commonly use two registers in a synchronization chain to minimize the
occurrence of metastable events, and a standard of three registers provides better
metastability protection. However, synchronization chains with two or even three
registers may not be enough to produce a high enough MTBF when the design runs at
high clock and data frequencies."
 
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