lty
Junior Member level 3
input clk, rst;
input [255:0] din; //input data；
input vld_in； //input data valid flag；
input sop_in; //input data packet start flag
input eop_in; //input data packet end flag
input [4:0] num_in; //the valid byte number of input data；such as 1：din[255:248] is valid, 2：din[255:240]is valid；32：din[255:0]is valid；
output [255:0] dout; //output data
output vld_out; //output data valid falg
output sop_out; //ouput data packet start flag
output eop_out; //output data packet end flag
output [4:0] mod_out; //output data valid byte number of the packet, it is valid when eop =1;
As it is showed in the upper, every clock, the valid data(the valid number is 0~32) enter, we need pack the input data into 32 byte data and output them.
My idea is the following:
reg [4:0] num_res;
always@(posedge clk)
if(rst==1)
num_res<=0;
else if( vld_in==1 )
num_res<= num_res+num_in;
always@(posedge clk)
if(rst==1)
data_res <= 0;
else if( num_res+num_in<=32 )
for(i=0;i<32;i=i+1)begin
if( num_res==i)
data_res <= {data_res[(256-1-8*i)+:8*i], din[(256-1-8*(32-i))+:8*(32-i)]};
else //if( num_res+num_in>32 )
for(i=0;i<32;i=i+1)begin
if( num_res==i)
data_res <= {din[0+:i*8], {(32-i){8'h0}} };
always@(*)
if( num_res+num_in>32 )
for(i=0;i<32;i=i+1)begin
if( num_res==i)
dout = {data_res[(256-1-8*i)+:8*i], din[(256-1-8*(32-i))+:8*(32-i)]};
always@(*)
if( num_res+num_in<32 )
vld_out = 1;
else
vld_out = 0;
Three questions:
1. Now the combination logic is too large, it is a 64 in 1 mux. Can we optimize it and use two or more clock to implement it?
2. Now the code can not be synthesized, because its operator data's width is not constant. Can we keep the code is concise and synthesized?
3. Can we make the code is parameterized, and implement the data pack for 16byte or 32byte or 64byte width input data?
Thank you, Welcome all suggestion!
input [255:0] din; //input data；
input vld_in； //input data valid flag；
input sop_in; //input data packet start flag
input eop_in; //input data packet end flag
input [4:0] num_in; //the valid byte number of input data；such as 1：din[255:248] is valid, 2：din[255:240]is valid；32：din[255:0]is valid；
output [255:0] dout; //output data
output vld_out; //output data valid falg
output sop_out; //ouput data packet start flag
output eop_out; //output data packet end flag
output [4:0] mod_out; //output data valid byte number of the packet, it is valid when eop =1;
As it is showed in the upper, every clock, the valid data(the valid number is 0~32) enter, we need pack the input data into 32 byte data and output them.
My idea is the following:
reg [4:0] num_res;
always@(posedge clk)
if(rst==1)
num_res<=0;
else if( vld_in==1 )
num_res<= num_res+num_in;
always@(posedge clk)
if(rst==1)
data_res <= 0;
else if( num_res+num_in<=32 )
for(i=0;i<32;i=i+1)begin
if( num_res==i)
data_res <= {data_res[(256-1-8*i)+:8*i], din[(256-1-8*(32-i))+:8*(32-i)]};
else //if( num_res+num_in>32 )
for(i=0;i<32;i=i+1)begin
if( num_res==i)
data_res <= {din[0+:i*8], {(32-i){8'h0}} };
always@(*)
if( num_res+num_in>32 )
for(i=0;i<32;i=i+1)begin
if( num_res==i)
dout = {data_res[(256-1-8*i)+:8*i], din[(256-1-8*(32-i))+:8*(32-i)]};
always@(*)
if( num_res+num_in<32 )
vld_out = 1;
else
vld_out = 0;
Three questions:
1. Now the combination logic is too large, it is a 64 in 1 mux. Can we optimize it and use two or more clock to implement it?
2. Now the code can not be synthesized, because its operator data's width is not constant. Can we keep the code is concise and synthesized?
3. Can we make the code is parameterized, and implement the data pack for 16byte or 32byte or 64byte width input data?
Thank you, Welcome all suggestion!
