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Problem with correct configuration of FPGA and PROMs (cascaded)

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Veronika

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I need to configure one FPGA and two Platform Flash memories.
I have found the following example: UG161.pdf, page 44, Figure 5-1.
There are two FPGAs - Master and Slave. But I am going to use Master FPGA only.
How changes the configuration setup in my case? Or I can simply ignore Slave FPGA in the Figure 5-1?
 

Just leave the slave FPGA device off. The platform flash allows for one device enabling a second device after the first has finished outputting all of it's data.
 
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