frozenone
Newbie level 3
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Need help on 16 bit counter, how do i write statement to check on my output count making sure it count from 0 to 15 and show error message.
library IEEE;
use IEEE.std.std_logic_1164.all;
entity counter_testbench is
end counter_testbench;
architecture counter_testbench of counter_testbench is
component counter
port ( count: out std_logic_vector(15 downto 0);
clk: in std_logic ;
reset: in std_logic;
end component;
signal count: std_logic_vector(15 downto 0);
signal clk: std_logic='0';
signal reset: std_logic='0';
begin
counter_circuit: counter
port map(count=>count,
clk=>clk,
reset=>reset);
clock
rocess
begin
wait for 10ns; clk<=not clk;
end process clock;
test _reset
rocess
begin
wait for 10ns; reset<='1';
wait for 10ns; reset<='0';
wait;
end process test_reset;
end counter_testbench;
library IEEE;
use IEEE.std.std_logic_1164.all;
entity counter_testbench is
end counter_testbench;
architecture counter_testbench of counter_testbench is
component counter
port ( count: out std_logic_vector(15 downto 0);
clk: in std_logic ;
reset: in std_logic;
end component;
signal count: std_logic_vector(15 downto 0);
signal clk: std_logic='0';
signal reset: std_logic='0';
begin
counter_circuit: counter
port map(count=>count,
clk=>clk,
reset=>reset);
clock
begin
wait for 10ns; clk<=not clk;
end process clock;
test _reset
begin
wait for 10ns; reset<='1';
wait for 10ns; reset<='0';
wait;
end process test_reset;
end counter_testbench;
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