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Gated clock for power saving

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virgorabbit

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How to implemented gated clock in SoC for power saving? Is the latch save for this implementation?
 

In physical Compiler, you can use insert_clock_gating command to do it
If your design has the following part figure, you can use clock gating technology do power saving

As you see, if the enable port is 0(or 1), the dff output will keep the original value despite how many clock edges have passed, so you can use clock-enable design described in the following picture to replace this design to save power
 

I think the future synthesizer will integrate this function and some others that are now optional
 

The attached document has some description about how to gate a clock

reliablely.


virgorabbit said:
How to implemented gated clock in SoC for power saving? Is the latch save for this implementation?
Click to expand...
 

in DC,first set _clock_gating_style,then elaborate design_name -gate_clock
 

u may write the code such as gate_clk = a & clk;
the DC ultra and PT access to the gate But the clock don't through the Mux
 

you can also insert clock gating yourself!
for exaple: system_clock = clock & en;
when en becomes low, the system will hold current state, because no clock is provided!
 

gogogo said:
you can also insert clock gating yourself!
for exaple: system_clock = clock & en;
when en becomes low, the system will hold current state, because no clock is provided!
Click to expand...

hi,
don't ever gate clock like this. Your design may become a victim of false triggering and Skew. Try to control the loading of the D i/p instead with the enable signal. Search on google and read some good pdfs about gating the clock. You will find lots of useful info there.

Best Regards
 

What problems could appear after insertion of the gated clock?

What about Enable signal for FFs? Should it be preserved?
 

Problem will be timing closure to the enable of the clock gate after expansion of Clock Tree synthesis. You should not expand the clock tree on the element which generates the enable to clock gate.
 

expansion of Clock Tree synthesis
Click to expand...
What is "expansion of Clock Tree"? Could you explain it please?

Gating cell is usually a Latch with AND gate. This Latch usually becomes transparent on the low phase of the clock. So, what problem might be with Enable to the clock?

Thank you
 

Glitches may occur for this reason more complex gating clock circuit are used such as those employing 2-flop synchronizers or other using asynchronous gates.
 

Have you seen flops in the netlist, which have both Enable signal and Gated Clock? Why these two signals are needed? It's not enough to use just Gated Clock or just Enable?
What situations both the Gated Clock and FF Enable are required?
 

@virgorabbit why do this during implementation or in SoC encounter . This can be well handled during synthesis stage.

Am not sure if SoC Encounter will not do it for you..
 
Last edited:

Is there a reason to use Enable signal for a flop, which has its Clock gated?
 

am not sure if i understand well.. but if you referring to the enable of the clock gating signal it is important cause that signal will identify whether to gate the clock or not depending on the switching of the clock which is essentially the idea thus saving us dynamic power.

@virgorabbit
Also i had a chance to read through SoC encounter and i see that it only understand clock gating and can clone / declone but not insert CG's
Pls correct me if my understanding on the above is incorrect
 

add the option gate-clock,when you run the design compile
 
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    ivlsi

    ivlsi

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the command is "compile -gate_clock" when your executing design compiler. But again this brings me back to my initial append.
This command works duirng synthesis and not in SoC Encounter
 

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