Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
the question is way to high level to have a precise answer - first which power leakage or dynamic
some optimizations / tricks mentioned below
- Clock Gating
- Annotating activity during synthesis
- MultiVt Synthesis
- use CPF / UPF to achieve more savings depending on design architecture and application for eg Power Shut Off
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.