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SDF vs SPEF -> why separated files?

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ivlsi

ivlsi

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Hi all,

Why do we need both SDF & SPEF files?

Would SPEF file be used for the Logic Synthesis?

Thank you!
 

Hi ivlsi,

In SDF , all the net delay are fixed. and in the SPEF , all the net delay has dependent on the capicatance and resistance of the net. What I mean to say - in the SDF - delay values are present but in the SPEF - cap and res value are present. So if you are providing the SPEF , then tool has to calculate the delay value using cap and res value.

i hope you got my point.

Please refer the following post - for more details of SDF and SPEF.

SDF part 1

Different file format

Let me know in case you have any followup questions
 

SPEF file provides capacitance and resistance only, but signoff sdf is generated using some tool specific algorithms bases on SPEF and other factors like loading, PVT, etc. SDF contains delay values, SPEF contaings resistance and capacitance values. Pre layout , only SDF files are used for timing analysis, which are calculated again using .lib files where timing information for standard cells are present as well as wire load model. Post layout, RC is extracted and more realistic interconnect delays can be calculated based on SPEF file. These delays will be reflected in signoff SDF when SPEF files are used.
 
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    ivlsi

    ivlsi

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signoff sdf is generated using some tool specific algorithms bases on SPEF and other factors like loading, PVT, etc. SDF contains delay values
Click to expand...
Why to translate SPEF to SDF? Do the tools deal with SDF better than with SPEF?

Pre layout , only SDF files are used for timing analysis
Click to expand...
Why should STA be performed in the Pre layout stage? What's the sense for doing that? Why not to just relay on the synthesis tool results?

Thank you!
 

hi ivlsi,
generally, SDF be used for simulation, it save many time to calculating timing by read SPEF (cap + res) to have nets delay, and main reason that simulation tool can't read SPEF because cap+res information are not useful.
about pre layout stage, you have no real PnR wire and any information to extract SPEF --> you just have 1 choice : use SDF (by extracted from STA with models-such as wireloadmodel)
 
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    ivlsi

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