Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how this LNA gain changed when input increase?

Status
Not open for further replies.
L

luciforlove

Member level 1
Member level 1
Joined
Sep 12, 2012
Messages
41
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,288
Activity points
1,535
234.png
here is the schematic.
2 at41485 as amplifier
at41485 1dB point is 18dBm when ic=40mA
on this schematic's instruction,it is said the LNA's 1dBpoint is 7dBm
but when i test it with Network Analyzer
S21 is 28dB when input is -20dBm,thats right
but when input is -10dbm s21=-20dB
when input is 0dbm,the gain is as low as 9
i really which part of this schem make this happen?how it works?and why design like that?
ps :Attached Thumbnails is not right ,idont know how to delete it
 

Attachments

  • QQ截图20121124131943.png
    QQ截图20121124131943.png
    46.6 KB · Views: 152
Last edited:

luciforlove said:
View attachment 83388
here is the schematic.
2 at41485 as amplifier
at41485 1dB point is 18dBm when ic=40mA
on this schematic's instruction,it is said the LNA's 1dBpoint is 7dBm
but when i test it with Network Analyzer
S21 is 28dB when input is -20dBm,thats right
but when input is -10dbm s21=-20dB
when input is 0dbm,the gain is as low as 9
i really which part of this schem make this happen?how it works?and why design like that?
ps :Attached Thumbnails is not right ,idont know how to delete it
Click to expand...

The P-1 dB is usually defined at amplifier output. Applying 0 dBm to LNA INPUT can even kill the device! LNAs have typically much lower P-1 dB than other amplifiers, and it is important not to overload their INPUT if one wants the device to have a low NF.
 
With -20 dBm input and your measured +28 dB gain, the second AT41485 is already past it's 1 dB compression point of +7 dBm (its output power is +8 dBm). As you increase the power, you are driving that further into compression and realizing less and less gain.

For -10 dBm input, you're seeing a gain of +20 dB, which means the output power of the second AT41485 is +10 dBm - which is well beyond it's P1dB point, so gain is compressed.

With the 0 dBm input both AT41485's are in compression.

For this circuit to work reasonable linearly, you should limit the input power so that the output power of the second AT41485 is at least 10 dB below it's P1dB point. Probably no higher than -30 dBm input.
 

pstuckey said:
With -20 dBm input and your measured +28 dB gain, the second AT41485 is already past it's 1 dB compression point of +7 dBm (its output power is +8 dBm). As you increase the power, you are driving that further into compression and realizing less and less gain.

For -10 dBm input, you're seeing a gain of +20 dB, which means the output power of the second AT41485 is +10 dBm - which is well beyond it's P1dB point, so gain is compressed.

With the 0 dBm input both AT41485's are in compression.

For this circuit to work reasonable linearly, you should limit the input power so that the output power of the second AT41485 is at least 10 dB below it's P1dB point. Probably no higher than -30 dBm input.
Click to expand...
at41485 1dB point is 18dBm when ic=40mA
and the schematic instruction says <the preamplifier:eek:utput power, 1dB compression is 7dBm >
it means the whole lna 1dBpoint ,i think ,but "output power" means when output is 7dbm,the lna is into compression?or input 1dbpoint is 7dbm?
 

The datasheet mentioned clearly that the output power at P1dB is 18.5dBm, and the gain at P1dB is 14dB.
P1dB is the output power when the amplifier is at the 1dB compression point, so in your case P1dB of the LNA is 18.5dB.
 
The datasheet specifies +18 dBm at 2 GHz frequency and with I.c = 25 mA, and V.ce = 8 V. But the P1dB will certainly change with biasing conditions and with the operating frequency. The schematic notes a P1dB of +7 dBm, and the test data shows a saturated power of 9 or 10 dBm, so both of those point to a P1dB of approximately +7 dBm for this particular implementation at this operating frequency.

Although this is a little speculative since we don't know the frequency, and the OP indicates there is an error in the posted schematic.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top