Analog to Digital Converter VHDL Code

Hey All!

I need to write VHDL Code for ADS8558.
Its a 16-, 14-, 12-Bit, Six-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER.

https://www.ti.com/lit/gpn/ads8558

But so far I am unable to figure out how should I do it.
I have Xilinix ISE 10.1 and the board I am using is Virtex2PRo.

So Please Help Me in Same.

Thanks and Regards

Well that document has all the timing diagrams you need. What code have you written so far?

TrickyDicky said:

Well that document has all the timing diagrams you need. What code have you written so far?

Click to expand...

Hey Thanks for Consideration.

Actually I am unable to start off.
Since I am unable to decide about How Should I Model Its Different Components
Like its Control Logic, Successive Approximation Register and .....

So Any Help in That Direction Would be Highly Appreciated

Thanks and Regards

Are you trying to design a simulation model for the ADC, an interface to the ADC, or an actual ADC?

ADC is an analog device. You can implement it in FPGA mostly (Except Some specific ADC).

joelby said:

Are you trying to design a simulation model for the ADC, an interface to the ADC, or an actual ADC?

Click to expand...

I don't Know Exactly. Since It was a task thas has been Assigned by my seniors.
Since I was Clueless So I Posted Here.

But as far as I know it would be a simulation Model.

Any Ideas how to proceed???

Thanks and Regards

May i ask you need the simulation model for what?

You initial post suggests that your assignment is to write an interface for the ADC as synthesizable code, to control the ADC in a real hardware setup. Because the ADC supports different interfaces (serial/parallel) and operation modes, you should specify the intended operation condition first.

joelby said:

Are you trying to design a simulation model for the ADC, an interface to the ADC, or an actual ADC?

Click to expand...

Yes

I am trying to build a Simulation Model

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FvM said:

You initial post suggests that your assignment is to write an interface for the ADC as synthesizable code, to control the ADC in a real hardware setup. Because the ADC supports different interfaces (serial/parallel) and operation modes, you should specify the intended operation condition first.

Click to expand...

It would be just a Simulation Model.

You can make your simulation model as comprehensive or as minimalistic as you need. If the code you want to test it against only ever implements one transfer mode, you don't need to bother implementing them all - just get it to generate random data (or a mathematical function, or a test vector from a file) and send it out using the timing diagram as a guide. The code doesn't need to be synthesisable, so you can use delays (#1 etc.) to make the timing match the data sheet exactly.

If you want to go a bit further you could implement the SPI interface too, and then all of the output modes.

If you want to go all the way, you could also model the analog transfer function (DNL, INL, etc.).

What's right will depend on exactly what you want to test with the model.

ishailesh said:

Hey All!

I need to write VHDL Code for ADS8558.
Its a 16-, 14-, 12-Bit, Six-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER.

https://www.ti.com/lit/gpn/ads8558

But so far I am unable to figure out how should I do it.
I have Xilinix ISE 10.1 and the board I am using is Virtex2PRo.

So Please Help Me in Same.

Thanks and Regards

Click to expand...

you are trying to build Simultaneous Sampling SAR ADC which has integrated DAC inside.by looking at datasheet circuit, it looks like fully digital device but in fact its analog/digital hybrid. one half of SAR converter is mostly digital, since it uses registers. but input to the converter is analog (to input any signal you need sample and hold circuit, which uses a capacitor and Opamp). although instead of capacitor at input they use a multiplexer and track and hold circuit; i have no idea how that works, but maybe it is possible to avoid a capacitor. second half of SAR converter is mostly analog. because inside the second half there is DAC, which is purely analog device (resistor R2/R ladder and Opamp ). so if you are going to create some magic code inside your fpga which will serve as Simultaneous Sampling SAR ADC, i'd say it's impossible.
one way is to use FPGA's logic in conjunction with analog components.analog components will be attached to the board externally via cable, or sort of that.but imagine how slow your adc would become, anyway it would work, to sample 100 k samples per second; and digitize it. a more elegant way could be to use an FPGA support chip which is a Hybrid of Analog and Digital (like this PSoC 5 https://www.cypress.com/?rID=38416). in this case, you would ask me how to program it, well, if in FPGA you would go something like
always @(posedge clock )
begin
something something
end

on PSoC 5 you may do something like this
Analog
begin
something something
end

honestly i have never done that and not sure how it works. some book was describing that when verilog was created, they created analog programming also, it's just the manufacturers who could not succeed to create a good analog device, decided to jump onto digital only.

OR!!!

you can buy an fpga which has a built in ADC DAC and all of your problems will be solved at once)) however avoid sigma delta adc since it's slow. integrators and tracker adc s are good, but badly sencitive to frequent change in voltage. Successive approximation ADC is the only legendary converter which is compact, and has no care of frequancy or something, however it has it's own speed and can not go faster than that. flash ADC is the fastest, but needs 256 opamp comparators and dozens of resistors + huge encoder to grab all 256 outputs and make 8 bits out of it.