Cadence Encounter doesn't fix hold violations?

Hi everyone,
please help me with the next problem:

I'm designing a digital IC based on FPGA-verified source code using Cadence tools: Encounter for P&R and optimization and Incisive simulator (NCSim may be the second name) for checking the resulting waveforms.
After P&R, in post-route stage, I optimized design using the next commands:

optDesign -postRoute
optDesign -postRoute -hold

and the results are:
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.021 | -0.021 | 0.044 | N/A | N/A | N/A |
| TNS (ns):| -1.751 | -1.751 | 0.000 | N/A | N/A | N/A |
| Violating Paths:| 356 | 356 | 0 | N/A | N/A | N/A |
| All Paths:|3.64e+05 |2.45e+05 |1.19e+05 | N/A | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
+--------------------+---------+---------+---------+---------+---------+---------+
| Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| 0.031 | 0.038 | 0.031 | N/A | N/A | N/A |
| TNS (ns):| 0.000 | 0.000 | 0.000 | N/A | N/A | N/A |
| Violating Paths:| 0 | 0 | 0 | N/A | N/A | N/A |
| All Paths:|3.64e+05 |2.45e+05 |1.19e+05 | N/A | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+

I know that setup violations were not fixed correctly, but hold were.
After that, I extracted the resulting netlist and SDF file and annotated them to simulator, and there are more timing violations in it's log file, but only HOLD. I think that setup violations were fixed decreasing the clock frequency in testbench, but, of course, HOLD not.

A part of ncsim.log file:
Warning! Timing violation
$setuphold<hold>( posedge CK &&& (ENABLE_RB === 1'b1):3236050 PS, negedge E &&& (ENABLE_RB === 1'b1):3236050 PS, 1.0 : 10 PS, 1.0 : 10 PS );
File: ./uk65lscsp10bbrccs_sdf30.v, line = 33170
Scope: :UUT.bis64.B_E.\tmp_reg[33]
Time: 3236050 PS


Warning! Timing violation
$setuphold<hold>( posedge CK &&& (ENABLE_RB === 1'b1):3236050 PS, negedge E &&& (ENABLE_RB === 1'b1):3236050 PS, 1.0 : 10 PS, 1.0 : 10 PS );
File: ./uk65lscsp10bbrccs_sdf30.v, line = 33170
Scope: :UUT.bis64.B_E.\tmp_reg[34]
Time: 3236050 PS

How can I fix hold violations in encounter? What I need to do? Please note, the program says that there are no hold violations in design.

Thanks in advance,
Kuxx.

Did you see whether they were any errors during the sdf annotation log.
Please check whether sdf annotation has happened or not.

mail4idle2,

ncelab log doesn't contains errors and warnings, I checked.
write_sdf command with -precision <value> parameter in Encounter provides sufficient accuracy. There should be no loss of significant digits and rounding errors in SDF file.

Problem is not solved yet.

I am not talking about ncelab log. Please c heck sdf annotation log.

mail4idle2,

SDF file annotates during elaborate process (ncelab).

ncelab: Memory Usage - 32.9M program + 3094.5M data = 3127.4M total
ncelab: CPU Usage - 11.7s system + 214.7s user = 226.4s total (311.1s, 72.8% cpu)
ncelab: ANNOTATION Time - 32.9s

There is no SDF annotation warnings in log.

Hi Kuxx,

Kuxx said:

How can I fix hold violations in encounter? What I need to do? Please note, the program says that there are no hold violations in design.

Click to expand...

encounter won't try to fix hold violations if it doesn't think that any exist. Are you simulating and implementing against the same technology library? I.e. is the setup and hold window for the flop that encounter sees the same as the timing check in the simulation library?

Best,
sharted

- - - Updated - - -

Another thought: what analysis views are you using for the implementation? single, bcwc or mmmc? How does this relate to the delays that you use for the back annotated simulation (MINIMUM, TYPICAL or MAXIMUM)? If you're implementing with a single analysis view and simulating with MINIMUM delays, you could see what you're seeing.

Best,
sharted

sharted,

I performed single analysis as you said and used MINIMUM delays from SDF file during annotation. There was no annotation warnings in this process, as usual. This didn't solved the problem, and there are a lot of hold violations in simulation log, nevertheless.
I would like to pay your attention at the fact that there are N/A result of timeDesign command for reg2out, in2out, clkgate for Setup and Hold checks both (see my 1st post). Could this affect on optDesign algoritm results and leave the hold violations unfixed? What can I do to constrain design correctly? In the SDC file I only created clock (create_clock) for the input pin.

Thanks in advance,
Kuxx.

Hi Kuxx,

I think the N/A entries come from the fact that either you have no reg2out paths, in2out paths or clock gates, or they're not constrained. Can you post some more details of your design? A list of inputs/outputs and the SDC file you're using? What happens if you simulate having annotated with MAXIMUM delays?

best,
sharted.

sharted,

my design is special data coder core with LVDS and ring oscillator for clock sourcing. Clock source (RO, LVDS) is selected by multiplexer. There is only one clock in design core, and I need to maximize clock frequency without setup/hold violation involving. This is the signature of digital core module:

module coder(C, CP, R, GP, D, VD, START, Q, QEND, QKF, QTR);
input C, CP, R, GP, D, VD, START;
output [18:1] Q;
output QEND, QKF;
output [4:1] QTR;
endmodule

The C input is clock signal, I synthesize clock tree for it.

My SDC file is:

create_clock -name "CLKFAST" -add -period 10.00 -waveform {0.0 5.00} [get_pins {cs/C}]
set_clock_gating_check -setup 0.0
set_dont_use [get_lib_cells uk65lscsp10bbrccs_100c25_tc/ADFM0NA]
set_dont_use [get_lib_cells uk65lscsp10bbrccs_100c25_tc/AN2M0N]
set_dont_use [get_lib_cells uk65lscsp10bbrccs_100c25_tc/AN3M0N]

etc...

When I sumulating my final netlist with MAXIMUM delays I see some SETUP errors along with HOLD too.

I suppose my SDC is incomplete, and this is the reason of design timing problems. In this case, what I need to add to my SDC file?

Thanks in advance,
Kuxx.

Hi Kuxx,

the first thing I think you need to do is specify input and output delays for your inputs and outputs. You should be able to find out what these are from the blocks that interface to yours that have already been implemented. Any blocks that haven't been implemented, you should be able to agree on a value with the designer responsible.

The second thing I would do is try to use a bcwc analysis for the implementation rather than a single view.

hth,
sharted.