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Dynamic Reconfigurable FPGA s - Current technology and trends

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gnrbyrm

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i have to prepare detailed project for my last year in 2 months. And My knowledges about FPGAs and embedded systems are not enough . So, i need some documents to learn the subject. Especially i should underline the new trends and current technologies of FPGAs implemented by using reconfugiration features of them. hopefully, you will help me :)
 

Are you trying to write a paper on the current state of reconfigurable computing (as in partial reconfiguration) or develop an FPGA design that demonstrates it? Maybe a combination of both?

If your writing a paper you can read about Xilinx's solution in documents on their website.

If your're planning on implementing something I'd suggest you rethink your project topic. There's a reason pretty much only military or researchers use this feature. It's not easy to implement a design with partial reconfiguration.

Regards,
-alan
 

No, no i just should write 20 pages of researches . So thank you for suggestion. But i examined xilinx website , i coldnt find needed knowledges concerning with my topic. Maybe i should try it again. Do you propose another website for me . So i need to fill 20 pages of A4 :D







ads_ee said:
Are you trying to write a paper on the current state of reconfigurable computing (as in partial reconfiguration) or develop an FPGA design that demonstrates it? Maybe a combination of both?

If your writing a paper you can read about Xilinx's solution in documents on their website.

If your're planning on implementing something I'd suggest you rethink your project topic. There's a reason pretty much only military or researchers use this feature. It's not easy to implement a design with partial reconfiguration.

Regards,
-alan
Click to expand...
 

Look again it might be hard to find. Try searching for "partial reconfiguration" as they actually support this feature now. They really began supporting this when they obtained PlanAhead as they could lock down the interface routing/placement for the boundary of the reconfigured logic. Prior to that they supported it in the bit file but it was very difficult to lock the interface down without resorting to specific placement and directed routing constraints.

Regards,
-alan
 
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