Generating a 78MHz clock from a 100MHz base clock

I have to generate a 78MHz clock (duty cycle 0.5 or 0.7) from a 100MHz base clock (duty cycle 0.5) using VHDL language (so the ratio is 200/156). I know that I can use DCM, PLL or similar, but at this moment (unfortunately) I just can't.

Therefore I thought to use (excluding any DCM or PLL) a simple frequency divider, but in this case I also know that the frequency can be divided only by integer numbers (and minimum 2, because I would use counters to do that - and In my case I have to divide the base clock by 1,2820512820512820512820512820513...).

So I have no idea how to realize that without using any DCM or other stuff... I thought to divide the 100MHz clock in smaller frequencies (like 50MHz, 25MHz etc.) and adding them (50+25+3 for example), but is this the right way (logically I don't think so)?

So, have you some suggests?

PLL blocks of recent FPGAs (e.g. from Altera and Xilinx) can easily do what you want, because they expose an input, feedback and output scaler. Review the user manuals and you'll see how.

I presume you want a clean 78 MHz output clock, not 78 MHz generated by skipping part of the 100 MHz clock pulses as a digital clock generator (DCO) would do. If so, you need an analog oscillator component, a VCO, which is available with PLL blocks but not in pure digital logic.

FvM said:

PLL blocks of recent FPGAs (e.g. from Altera and Xilinx) can easily do what you want, because they expose an input, feedback and output scaler. Review the user manuals and you'll see how.

I presume you want a clean 78 MHz output clock, not 78 MHz generated by skipping part of the 100 MHz clock pulses as a digital clock generator (DCO) would do. If so, you need an analog oscillator component, a VCO, which is available with PLL blocks but not in pure digital logic.

Click to expand...

I can't use PLL or similar (I have said that in my first post ^_^), so I have to find another way...

I can't use PLL or similar (I have said that in my first post ^_^)

Click to expand...

And you can't do with purely digital circuits. (I have said...).
Either consider which kind of analog frequency generation circuits is feasible for your application, or give it up.

why cant you use PLL or DCM?

Unfortunately I'll receive the FPGA (Digilent Nexys 2 1200k) in one month, but I need a temporary solution right now

Temporary solution options: just simulate the design, no physical hardware required. Or use and external PLL. Or go do something else during the month and then use the DCM when you get that spartan-3e board. Or give up.

Or do it with logic and take the horrible jitter as a nice experience to learn about the effects of horrible jitter.

Anyways, I don't quite see the practical issue. If you don't have the real hardware yet, you don't have a system running on 100 MHz yet. So just use whatever you happen to have lying around that can get you in the 78 MHz area. You can always worry about the details once you get the board.

If I don't care about the jitter (for now), how can I generate the frequency desired?

To get and idea about the requirements, what's the usage of the 78 MHz clock?

HyperText said:

If I don't care about the jitter (for now), how can I generate the frequency desired?

Click to expand...

If you really don't care about jitter...use a pulse swallower.
As an example use a 100MHz counter that counts from 0-99 at 22 of those counts generate a signal to gate the clock. Your average frequency over 100 clock cycles is now 78 MHz.

Regards,
-alan

LOL! You are an evil person. But hey, he did say he didn't care about jitter. ;-) And your solution is 1) simple and 2) gives an average of 78 MHz, all within spec.

If you really don't care about jitter...use a pulse swallower.
As an example use a 100MHz counter that counts from 0-99 at 22 of those counts generate a signal to gate the clock. Your average frequency over 100 clock cycles is now 78 MHz.

Click to expand...

That's the DCO solution which I assumed as unwanted in post #2 (e.g. because it doesn't keep the duty cycle specification), a "fractional" frequency divider skipping each fourth or fifth pulse up to 22 per 100. It can perfectly work, if the generated clock is further divided afterwards, e.g. in case of an oversampling UART clock.

Oh wait, I see he did specify duty cycle. Darnit.