Altium Bus: Duplicate Net Names

Hi,
I have 2 Schematic-Documents in a Project-Workspace.
In each sheets I placed a bus and named the wire which is connected with the bus and busentry with "Test1".
When I compile the document i get following error:
"Duplicate net names wire Test1"

Thanks for your help

Hi,

if it is possible attach the screen shot for what you are trying.
also check is there any same pin name part.

Please verify "Net Identifier Scope" also...

One thing that got me recently is that you can't just have a yellow port named Test[1..x] and a thick blue wire, and off that a singleton net Test1. You must also have a net label on the thick blue bus wire named Test[1..x].

It's not realizing that Test1 and the port are related. Singleton net to named bus net is based on the common root name 'Test' (the little 30 degree exits aren't required.) However the entry/port name is arbitrary (doesn't need to match even if this is a good practice to keep you sane) and the only way it knows the port is related to the bus is because they touch graphically.

So you have to have all three: named port, named bus, named wire.

Of course the Altium sch compiler doesn't give any meaningful warning when you do this, it just tries to add two identical nets to the PCB in your ECO and barfs on the second (and fourth, and sixth, ....) line when validating.