[Help] write a complete RTL description for a ROM module

TrickyDicky said:

what have you written so far?

Click to expand...

module and_or(
in1,
in2, 
in3, 
in4, 
out 
); 
  input in1;
  input in2;
  input in3;
  input in4;
  output out;
  wire in1,in2,in3,in4;
  wire tmp1,tmp2; // temp var
  and(tmp1,in1,in2);
  and(tmp2,in3,in4);
  or(out,tmp1,tmp2);
endmodule

`timescale 1ms/1ms
`include "lab1.v" //include lab above
module tb_lab2;
  reg in1,in2,in3,in4;
  wire out;
  initial begin
    $monitor("in1=%b\tin2=%b\tin3=%b\tin4=%b\tout=%b", 
    in1, in2,in3,in4,out);
    in1=1;
    in2=1;
    in3=1;
    in4=1;
   #1 in1=1;
   #1 in2=0;
   #1 in3=1;
   #1 in4=1;
end
endmodule

ads_ee said:

Code:

What exactly don't you understand about this code. Please be specific.

FWIW it computes the following boolean equation: out = (in1 AND in2) OR (in3 AND in4)
[/QUOTE]
thanks u so much !In above lab, I have designed success.
and thís is result ficgure
[ATTACH=CONFIG]82465._xfImport[/ATTACH]
[QUOTE="ads_ee, post: 1160147, member: 486795"]
[CODE]
`timescale 1ms/1ms
`include "lab1.v" //include lab above
module tb_lab2;
  reg in1,in2,in3,in4;
  wire out;
  initial begin
    $monitor("in1=%b\tin2=%b\tin3=%b\tin4=%b\tout=%b", 
    in1, in2,in3,in4,out);
    in1=1;
    in2=1;
    in3=1;
    in4=1;
   #1 in1=1;
   #1 in2=0;
   #1 in3=1;
   #1 in4=1;
end
endmodule

This TB code just applies a 1 to all the inputs at time 0 and changes only in2 to 0 2ms into the simulation.

Regards,
-alan

Click to expand...

ads_ee said:

Didn't catch this earlier, but you forgot to add your and_or instance in the TB. There is nothing driving the out signal.

Put the and_or instantiation between the end and endmodule statments.

Regards,
-alan

Click to expand...

`timescale 1ms/1ms
`include "lab1.v" //include lab above
module tb_lab2;
  reg in1,in2,in3,in4;
  wire out;
  initial begin
    $monitor("in1=%b\tin2=%b\tin3=%b\tin4=%b\tout=%b", 
    in1, in2,in3,in4,out);
    in1=1;
    in2=1;
    in3=1;
    in4=1;
   #1 in1=1;
   #1 in2=0;
   #1 in3=1;
   #1 in4=1;
end

module and_or(
in1,
in2, 
in3, 
in4, 
out 
); 
  input in1;
  input in2;
  input in3;
  input in4;
  output out;
  wire in1,in2,in3,in4;
  wire tmp1,tmp2; // temp var
  and(tmp1,in1,in2);
  and(tmp2,in3,in4);
  or(out,tmp1,tmp2);
endmodule


endmodule

ads_ee said:

You can't embed a module inside another module. That isn't how you add an instance of a module. I think you might want to read some of the verilog tutorials on the net to supplement your class.

I also noticed that you have no function definition for the and and or statements. Are these supposed to be functions or are they instances of a module and... and a module or... in a library or something?

Well for both the new module and the and and or modules (if they aren't functions)...

The syntax is supposed to be:
module_name instance_name (the_ordered_list_of_assignments_separated_by_commas);

e.g.
and u_and (tmp1, in1, in2);

I prefer named association though:

---

Code Verilog - [expand]
1
and u_mygate (.out(tmp1, .a(in1), .b(in2)); // assuming the [B]and[/B] module ports are: module and (output out, input a, input b)

---

Think of instances as components on a PCB and the wire declarations are your net names of the routing between components. So you need component the_u_number_identifier (list_of_the_ connections) to hook up the board.

Regards,
-alan

Click to expand...

ads_ee said:

I gave you an example with the and gate...

I'm not going to do your homework for you.

Regards,
-alan

Click to expand...

ads_ee said:

I gave you an example with the and gate...

I'm not going to do your homework for you.

Regards,
-alan

Click to expand...

module rom_using_case (
  address , // address input
  data    , //  data output
  read_en , // read enable
  clk        //Clock
  );
  input [3:0] address;
  output [7:0] data;
  input read_en;
  input clk;
  
  reg [7:0] data ;
         
  always @ (clk or read_en or address)
  begin
    case (address)
      0 : data = 10;
      1 : data = 25;
      2 : data = 34;
      3 : data = 66;
      4 : data = 98;
      5 : data = 163;
      6 : data = 178;
      7 : data = 184;
      8 : data = 196;
      default : data =0;
    endcase
  end
  
 endmodule

ads_ee said:

I see some pretty basic stuff that you don't seem to have grasped.

I think you should invest some time in reading some of the basic tutorials on Verilog that are around on the web. Try google with "Verilog tutorial"

Code:

  always @ (clk or read_en or address)
  begin
    case (address)
      0 : data = 10;
      1 : data = 25;
      2 : data = 34;
      3 : data = 66;
      4 : data = 98;
      5 : data = 163;
      6 : data = 178;
      7 : data = 184;
      8 : data = 196;
      default : data =0;
    endcase
  end

In that block of code it looks like you want to have a registered data output, but you wrote the always block as combinatorial. You also included the signal read_en that you aren't even using in the block.

Hint1: in a registered always block you don't need to include any signals other than the clock and if required an asyncrhonous set/reset as the block should only be scheduled on a clock edge or when the asynchronous set/reset goes active. Try looking over a Verilog tutorial for ideas on how to do this.
Hint2: use an if statement to decide what to do when the read is enabled or disabled.

you should define the width of those decimal numbers in the case statement for both the address selected and the data assignment. What you have will compile and synthesize but you'll see a lot of warnings due to the width conversion as integers have a default of 32-bits and they will be truncated to fit the data width and the address comparison width.

Regards,
-alan

Click to expand...

Write a complete RTL description for a ROM module b
a one-dimensional array and a Verilog reg data type and a case statement. 
and testbench for thís lab