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parametrized OR-gate

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eng.amr2009

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Hi all,

I have this code in VHDL which describes a generic OR-gate which is used to OR all bits of a vector:

Code: 
entity var_or is
generic(
  width : integer :=8
);
port(
  InVector : in std_logic_vector(width-1 downto 0);
  VecOred : out std_logic
);
end var_or;

architecture behav of var_or is

begin

process(InVector)
  variable vResult : std_logic;
begin
  vResult := '0';
  for i in 0 to width-1 loop
    vResult := vResult or InVectgor;
  end loop;
  
VecOred <= vResult;

end process;

end behav;


I need to design the same generic OR-gate in verilog. I use this component intensively. I instantiate it many times with different widths.

Thanks in advance.
 

The intended operation can be achieved in Verilog with a unary reduction operator without instantiating a module, a logical reduction operator is also provided with VHDL 2008. In previous VHDL versions, an or_reduce() function has been offered by the std_logic_misc package.
 
Just to clear up what FvM said.

Code: 
signal a : std_logic;
signal b : std_logic_vector;

--VHDL 1993
a <= or_reduce(b);

--VHDL 2008
a <= or b;
 
As the OP wanted to know the verilog OR reduction...

Code: 
wire a;
wire [31:0] b;

// verilog or reduction
assign a = |b;

Regards
-alan
 
Thanks alot people for your help :)

I have another question. In VHDL to initialize a 2-D array with all zeros we do RAM_ARRAY <= (others=>(others=>'0'))
How can we do the same in verilog ? I do it using for loop but I'm not sure if this is correct as for loops are not recommended.

Thanks in advance
 

As an example, this was used in a design I did quite a while ago to generate a start address lookup table. Works fine.

Code Verilog - [expand]
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generate genvar i;
 
  // Create a lookup table for the start addresses for the 24 deep buffers
  for ( i=0; i<pPORT_MAX; i=i+1 ) begin: ADDR_LUT
 
    assign start_addr_LUT[i] = (9'd24)*i;
 
  end // block: ADDR_LUT
 
  endgenerate


Regards,
-alan
 

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