Reset of syncronizing flip flops

The schematic misses a clock. How can it be complete?

The answer to your question depends. Consider the case, that R is asserted and deasserted before the (hidden) clock starts to work.

FvM said:

The schematic misses a clock. How can it be complete?

Click to expand...

There will definitely be a clock that will be connected with the clock pins of the two flipflops. Sorry that is not present in the schematic.

The answer to your question depends. Consider the case, that R is asserted and deasserted before the (hidden) clock starts to work.

Click to expand...

The schematic is for a active high reset.

FVM

What is your answer now?

Hi,

do you have a clock during active reset?

If no.
your ciruit will not work, because the two reset FFs will stay in undefined state. For this you need to do an asynchronous reset the two FFs. But if you do an asynchronous reset to the two FFs you do not need the AND gate, because you will produce a reset anyway because you reset the reset synchronizer.

If yes
If your reset pulse is longer than two clock cycles your circuit will work without connecting a reset to the two FFs.
But if you have a clock during reset, why do you need to assert the reset to the reset of the system asynchronous?
Why do you need the AND gate?
You can just synchronize the reset with the two FFs.


To my opinon you do not need the AND gate. I think you can use a different synchronizer.

regards

qieda

do you have a clock during active reset?

Click to expand...

why do you need to assert the reset to the reset of the system asynchronous?

Click to expand...

Can you please explain what you are trying to ask here? Which reset are you talking of when you write "to assert the reset" and which reset are you talking of when you write "the reset of the system asynchronous"? What system are you indicaing when you state "the reset of the system asynchronous"?

Why do you need the AND gate?
You can just synchronize the reset with the two FFs.

Click to expand...

The corresponding person was trying to synchronize the reset and so he stated that an AND gate can synchronize. Even synchronized reset can be produced by two FFs also. What are you trying to mean by stating "You can just synchronize the reset with the two FFs"?

To my opinion you do not need the AND gate. I think you can use a different synchronizer.

Click to expand...

Why do you want a different synchronizer? Is it that you want to synchronize the reset to provide the synchronized reset to the reset pins of the two flipflops in the diagram? Can you please explain what you wanted to mean?

FVM

I am still waiting for your answer. Please reply.

Hi,

your reset synchronizer is no "state of the art" reset synchronizer.
In my opinion there are better ways to do reset synchronizing.

But maybe I do not understand your application.
Why do you not do a standard way of reset synchronizing?

to your questions
to make wording clear.
the input of the reset synchronizer I call reset_in
the output of the reset synchronizer I call reset_sync

Here the new version:


do you have a clock during active reset? (question is still open)

If no:
your ciruit will not work, because the two reset FFs will stay in undefined state. For this you need to do an asynchronous reset the two FFs. But if you do an asynchronous reset to the two FFs you do not need the AND gate, because you will produce a synchonous reset output (reset_sync) anyway because you reset the reset synchronizer.

If yes:
If your reset pulse is longer than two clock cycles your circuit will work without connecting a reset to the two FFs.
But if you have a clock during reset, why do you need to assert the reset output (reset_sync) asynchronous?
You can just synchronize the reset input (reset_in) with the two FFs.

regards

do you have a clock during active reset? (question is still open)

Click to expand...

Sorry the answer to this question, somehow was missed. Yes, I have a clock during active reset. That clock will be connected to the clock pins of the two flipflops in the schematic that I drew at the beginning of this thread. Sorry, I did not drew the clocks there as flipflops definitely will have clocks.

to your questions
to make wording clear.
the input of the reset synchronizer I call reset_in
the output of the reset synchronizer I call reset_sync

Click to expand...

I have provided the name in my diagram. Can you please use my names of signals? Or, are you talking of an additional synchronizer by "reset synchronizer" here?

Regards

Thanks to qieda for elaborating the point about running clock during reset assertion. Post #24 answers all open points exactly. I also agree to the comment about better using the standard synchronizer circuit. As far as I see, the discussed circuit doesn't offer advantages. It surely fails, if the clock isn't running during reset signal assertion.

In my view, the thread can be paraphrased like:
"I designed a square wheel. Should I curve the edges?"

sun_ray said:

Or, are you talking of an additional synchronizer by "reset synchronizer" here?

Click to expand...

Every post has been referring to your circuit as a "reset synchronizer". Maybe you refer to it as something else, since it's not a very good reset synchronizer.

-alan

Sorry, I do not find your diagram.

I'm talking about your circuit when I'm talking about the "reset synchronizer"

regards

qieda

In post no. 1 there is a picture attached with that post. By diagram I mean that picture.

But if you have a clock during reset, why do you need to assert the reset output (reset_sync) asynchronous?

Click to expand...

The reset is wanted to be asserted asynchronously and hence we need to assert the reset output (reset_sync) asynchronously.

Why do you need the AND gate?

Click to expand...

In my diagram/picture there is a OR gate and no AND gate is there.

Can you please qieda answer my question? If you need more clarity please let me know.

Regards


FVM

- - - Updated - - -

FvM said:

It surely fails, if the clock isn't running during reset signal assertion.

Click to expand...

Can you please let me know what you are trying to mean here? I wrote that the schematic has a clock which is connected to the clock pins of the flipflops.

In my view, the thread can be paraphrased like:
"I designed a square wheel. Should I curve the edges?"

Click to expand...

This is not a correct phraphrase. It shows that your understanding is still vague but not as vague as it was about the post in last year when you replied the thread.

Regards

Click to expand...

I have provided the name in my diagram. Can you please use my names of signals?

Click to expand...

ok please
change "reset_in" into "R"
change "reset_sync" into "R_Q"
in my posts

I'm sorry I did not noticed you have a high active reset.
so please
change "AND" into "OR"
in my post


Here is the answer to your question
Please connect "R" to the reset of your input flip flops.

Personal comment
This is at least the second best answer
The best answer would be: Use a different reset synchronizer.
But to my understanding you do not want to here this answer.

Have a nice day.

qieda said:

Personal comment
This is at least the second best answer
The best answer would be: Use a different reset synchronizer.
But to my understanding you do not want to here this answer.

Have a nice day.

Click to expand...

It is good that you suggested for use of a different reset synchronizer. Thanks for such solutions and comments. But you are right that I need the answer of my questions on top of your suggestions.

Please connect "R" to the reset of your input flip flops.

Click to expand...

the reset value has to be 1 since you have high active reset

qieda said:

Here is the answer to your question
Please connect "R" to the reset of your input flip flops.

Click to expand...

But this will lead the synchronizing flipflops to metastability issue. Is not the better solution is to keep the reset pins of the flipflops unconnected? This is because the synchronizer present in the picture is necessary for generating a reset for the system. So there is no need to reset these flipflops.

Hi,

Yes, the first flip flop of the chain can become metastable.
This is the reason, why you have the second FF. This second FF will not be metastable.
So the reset output "R_Q" will be stable.

But:
The first FF can become metastable if you reset the flip flop like I would do.
And it can become metastable if you do not reset the flip flop like you want to do.
Because the "R" input is asynchronous to the clock.

If you do a reset of the two flip flops, your circuit will also work
- if you do not have a clock during reset or
- if your reset "R" is shorter than 2 clock periods.

In both cases a solution without reset may not work, because the state of the two synchronizer flip flops is undefined during power up.
So I think a reset would make your system more robust.


regards

If you have a flop without any reset you have 50% of the time the output will be 0 or 1, then till you external reset is not asserted your design will start randomly.

Personally, I prefer used a simple synchronizer, the flop has CK connected to system clock, Reset or Set pin connected to external reset, data pin connected to 1 or 0 dependent of the reset de asserted polarity.
And the output will be used as digital reset.
For the flops using the rising of system clock, the synchronizer will be on the falling edge of system clock.
And for the flops on the falling edge of system clock, an other synchronizer will be on the rising edge of system clock, to provide half cycle of margin for popragation.