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read and write data from/to ram of fpga

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electronical

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hello,how can use the ram of fpga ices?
i have a matrix 4x6 and i want write it to ram(dont use slice).
how can I do it?
 

Re: read and wrute dada from/to ram of fpga

Depending on your vendor, you can just create a RAM IP, and then instantiate that RAM component in your design. What tool/vendor are you using? (I don't know what "ices" means)
 
Re: read and wrute dada from/to ram of fpga

I wonder if the OP advocates the use of lsd to facilitate forum message decoding... One possible interpretation:

electronical when making sense said:
Hi! I would like to use an DDR ram module, external to the fpga. And just to clarify I do not want to use the block ram or fabric flip-flops. Furthermore I toss in the word "ices" (personal shorthand notation for slices) as a clue that I may or may not be using Xilinx fpga's.
Click to expand...

In which case you want to use the MIG (Memory Interface Generator) that you can access from core generator.






Or you meant something else, in which case do something different. A clear post would be a good start. ;)
 
Re: read and wrute dada from/to ram of fpga

mrflibble said:
I wonder if the OP advocates the use of lsd to facilitate forum message decoding... One possible interpretation:



In which case you want to use the MIG (Memory Interface Generator) that you can access from core generator.






Or you meant something else, in which case do something different. A clear post would be a good start. ;)
Click to expand...

thankyou,but how can i do it with out using core generator?
 

Re: read and wrute dada from/to ram of fpga

Would you care to define "it"? I am sure you have "it" clearly defined inside your brain, but so far it has not escaped it in the form of text.

Do you mean DDR? If yes, without MIG I'd say forget it. if you mean BRAM, use a BRAM primitive. if you mean something else, define it.
 

Re: read and wrute dada from/to ram of fpga

Which FPGA and which software are you using ?

In Altera and Xilinx, i've instantiated the RAM block using the built in core. Then made connections and allocated the pins. It worked fine.

If you want to do it without a core generator, then you'll probably have to work out the strobe signals etc, generate them and it should work just fine.

I did the above too, in an altera FPGA with an external RAM module. It was before i knew we could instantiate the RAM as a block.
 

Re: read and wrute dada from/to ram of fpga

ninju said:
If you want to do it without a core generator, then you'll probably have to work out the strobe signals etc, generate them and it should work just fine.
Click to expand...

You did that for external DDR/DDR2 ram? As opposed to SRAM? That sounds neat!

Then again, the random undefined bit-width 4x6 matrix probably isn't that big. So a simple ram using the flip-flops probably suffices. In which case the OP can use any boring old RAM module.

There we go, some example code for RAMs.
 

Actually, it was the first time i saw an FPGA. I wanted to model a microcontroller. It cam with a RAM module with a DIMM slot and there was an old RAM. I read the signals for it, saw the FPGA board connections, worked out the timings and did it after a long struggle. Its basically just a waste of time, i'd recommend using cores. Modelling a microcontroller took just a day after a week's theoretical design. Sorting this one out took a month or so.
 

electronical said:
hello,how can use the ram of fpga ices?
i have a matrix 4x6 and i want write it to ram(dont use slice).
how can I do it?
Click to expand...

You can use Coregenerator to generate a BRAM

good luck !
 

Maybe electronical doesn't like core generator, I dunno?

electronical said:
thankyou,but how can i do it with out using core generator?
Click to expand...

Although it's going to be hard... something that does use ices, but doesn't use slices, and without using core generator. Neat puzzle!

Anyways, just instantiate a BRAM already and be done with it. :p You can find BRAM instantiation templates in the "Xilinx FILL_IN_PART Libraries Guide for HDL Designs". For example: https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf ... see page 13 BRAM_SINGLE_MACRO.

Or as already states, if you want to use flip-flops, see the link in post #8. And if that doesn't fit with the requirements, kindly post clear requirements. :)
 
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