Common Emitter Amplifier Design

I want to calculate Vce and then proceed to choose a suitable resistance Re2 in this circuit : http://www.ecircuitcenter.com/Circuits/trce/Image02.gif , does anyone have any idea on how I can do it? Any help will be greatly appreciated.

I want the maximum output swing of +-5 so I would I set Vc = 5v, I also already have ( R1 || R2 ) = 42k, Rc = 20.2k, Re1 = 3.36, Ic = 5mA, Vcc = 10v , Beta = 200 (=> Gain = 6.). The value of Ic is just a value I randomly chose as a suitable value to design the circuit around, because I know that usually 1mA < Ic < 10mA .

use multisim simulator and put multimeter across Collector and emitter this will give you Vce.


press "+Give point" if you like:arrow:

First, if Ic=5mA, then the voltage across Rc is 100 volts.
Second, if Ic is 5ma, then the voltage across Re is 15volts.

Back to the drawing board.

jaysenghani said:

use multisim simulator and put multimeter across Collector and emitter this will give you Vce.


press "+Give point" if you like:arrow:

Click to expand...

I need the Re2 resistor value before I can simulate, that's why I want the Vce value.

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barry said:

First, if Ic=5mA, then the voltage across Rc is 100 volts.
Second, if Ic is 5ma, then the voltage across Re is 15volts.

Back to the drawing board.

Click to expand...

I set Vc = 5v, I also already have ( R1 || R2 ) = 52.5k, Rc = 5k, Re1 = 0.83k, Ic = 1mA, Vcc = 10v , Beta = 200 (=> Gain = 6).

The design guidelines say : 1)Write the maximum swing requirement for the output of the amp.
2)Choose a reasonable DC collector current for the first stage, IC1
3)Calculate the DC voltage for VCE1 by using condition (1)

I the think the max swing should be -5 < Vout < 5 .So what does that mean for VCE? All that means is that Vc = 5v, but that seems to say nothing about VCE.I have a feeling I should just take VCE to be 0v ( ie VBE = 0.6v & VCB = -0.6v ) so I can allow all the output voltage to swing that much, if I take


VE ( at DC ) = 5v
=> When Vout goes to -5

VE( at DC) + Vout(AC) = 0
VE( at DC) + Ve( AC) = 0

==> When Vout goes to 5v

VE( at DC) + Vout(AC) = 0
VE( at DC) + Ve( AC) = 0

If the maximum swing is -+ 5v

Re1 and Re2 determine the bias point (Along with R1 and R2). Re1 and Rc determine the AC gain.

barry said:

Re1 and Re2 determine the bias point (Along with R1 and R2). Re1 and Rc determine the AC gain.

Click to expand...

I know, AC gain = Rc/Re1 = 6

Re1 and Re2 will determine the bias point but I first need to pick a suitable value for Re2, and for that I will need to use KVL going around the output loop, and for that I need to get VCE.

If you know Rc, and you know your quiescent collector current, then that's all you need. You don't need Vce, you need Ve such that Ve/(Re1+R32)=Ic. And Ve is determined by the base bias (R1, R2).

barry said:

If you know Rc, and you know your quiescent collector current, then that's all you need. You don't need Vce, you need Ve such that Ve/(Re1+R32)=Ic. And Ve is determined by the base bias (R1, R2).

Click to expand...

But I need to pick the Re2 value carefully because it will help me better choose the capacitor Ce properly, I want to make sure I have all my components designed properly.Right now the values I've given together with a Re2 value of 3.9K give me a small signal gain of 6.7 when I simulate them on LTSpice ( which is good enough I guess ) , but when I try to connect it to my other Amp with a 1MicroF coupling capacitor, which is just a common collector buffer with a input resistance = 200K ( ie Rout(Amp) << Rin(Buffer) ) , I get a signal with gain 4 coming out of the buffer.

The buffer looks like : http://www.vk2zay.net/calculators/transistors/commonCollector.jpg

with R1 = 18k, R2 = 22K, Re = 1K and works well when simulated independently.

A few comments: Does the gain drop when you connect the output in simulation or in reality? What is the emitter capacitor (Ce)? That creates a high-pass filter. Does the gain drop at the collector of the first stage or at the output of the second stage? What frequency are you testing this at? The input to the second stage is a high-pass filter with a cutoff of about 16 Hz.

barry said:

A few comments: Does the gain drop when you connect the output in simulation or in reality? What is the emitter capacitor (Ce)? That creates a high-pass filter. Does the gain drop at the collector of the first stage or at the output of the second stage? What frequency are you testing this at? The input to the second stage is a high-pass filter with a cutoff of about 16 Hz.

Click to expand...

The output drops at the output of the amp when I connect the buffer to the end of the amplifier in simulation, I have not connected a load to the end of the buffer yet.

Ce = 10microF
Test_Freq = 1Khz

The output drops at the output of the first stage.

Vin(AC) = 0.1v peak to peak
Vout(Stage 1) = 0.4v (AC) + 5.28v (DC) <== This is the weird part, I don't know why there is a output has a DC component
The voltage at the collector is 5.04v (DC) + 0.4v(AC) so I would expect the coupling
capacitor to just remove the DC component but it has instead ADDED 0.2v to it.
Vout(Stage 2) = 0.4v (AC)

Your second stage is obviously loading the output of the first. Try changing the bias resistors on the buffer (R1, R2). Or, you could get really complicated and add some feedback around the whole thing.

barry said:

Your second stage is obviously loading the output of the first. Try changing the bias resistors on the buffer (R1, R2). Or, you could get really complicated and add some feedback around the whole thing.

Click to expand...

Yeah, I guess it was a loading problem, I increased the R1 and R2 resistors in the common collector amplifier to values over 100k and Re to 5k and the circuit simulated well.