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How to get clock latency value before CTS?

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hgby2209

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Currently, I pass my netlist & constraint to APR engineer to run a rough CTS then get clock slew report, and base on the skew report to set clock latency.

But if I don't want to run the rough CTS , how can I get the clock latency value?
 

During pre-layout stage, such as logic synthesis and pre-layout STA, you should treat clock signals as ideal nets, and set estimated values for clock skew and clock latency. The values can be general for the technology you choose, or your design requirement. It's bettter that the values are close to the actual after layout.
 

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Thanks!! carrie, I know what you talk about.
But I want to know how to estimated the value for clock latency?
 

It's not easy to estimate clock latency before CTS. But you check your clock spec for CTS, from that,you can get some information about final CT, such as:
how many level in CT, what kind of cell in CT, max fanout of cell in CT, then
you can roughly estimate clock delay .
 

There is no way. It's very design/tool/experience dependant. But normally, clock latency is not a big issue, it only affects your IO path in the chip. And IOs are normally fliped before they coming into or going out of the chip.
 

I need to give APR engineer the latency value as CTS spec.
if I can't estimate the value, how can APR engineer do the CTS?
 

apr designer may insert clock tree automatically, eg, socencounter. according to the design . of course ,you can estimate. I think you let tools automactical.
 

the lever number equal to log8(DFFsnumber_clk).
the latency equal to lever number X cllk_buffer's delay.
but it is too not accurate.
 

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