Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
"In #10 b = 0; the simulator will execute b = 0; after 10 units of time (like inertial delay). In b = #10 0; "0" will be assigned to "b" after 10 units of time (like transport delay)."
Answer to similar question also available at: https://only-vlsi.blogspot.com/2008/01/verilog-2.html
#10 b=0; execution of this command will be happened only after 10 time units (inter delay assignments)
whereas "b=#10 0;" command starts execution in "0" time units, but the value(0) is assigned to "b" only after 10 time units.(intra delay assignments)
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
