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Cut poly in TSMC 28nm

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srihari465

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Hi All,

Currently I am working on TSMC 28nm process, can anyone tell what's the use of a Cut Poly layer???

Regards
Sreeharii
 

I think it has got something to do with double pattern lithography.
 

There is no double patterning in TSMC 28nm. Cut Poly is meant to align narrow poly shapes (for short transistors) by cutting their width to the same size. I think it is needed by lithography process to neighboring poly shapes would have the same width.
 
Yes , its correct what Sergio told, TSMC 28nm is not using Double Pattern Lithography.But Cut masks are used only in DPL. Can you tell what exactly is the lithographic process used in TSMC 28nm.

Regards
Sreehariii.......
 
Are you sure that cut masks are used only in DPL? I'm not.
 

Nope, it is mentioned as "Double PO Cut" layer as far as I remember. ;)
 

Then we used different TSMC 28nm process... (but honestly I do not believe it)
 

Hm, so there is incoherence between DRD and layer usage document where I checked. But since there is no double patterning in TSMC28nm as far as I know, I would trust layer usage document and assume that in DRD is mistake in layer description.
 
Yes, its Double PO patterning

- - - Updated - - -

Hello, Can you please share some documents regarding 28nm process.I am currently working on it and facing much difficulty.Hope for help.
Thank you.
 

Prashanthanilm said:
Yes, its Double PO patterning

- - - Updated - - -

Hello, Can you please share some documents regarding 28nm process.I am currently working on it and facing much difficulty.Hope for help.
Thank you.
Click to expand...

Yup, Its mentioned as 'Double PO patterning' in DRD and 'Poly double cut' in Layer Usage Description file. Read the Design Rule Document it contains every info you wanted....
 

Cut poly is used to reduce cell spacing. Instead of following the regular DRC rules, by using cut poly, you can have a single poly shared between two devices with cut poly inserted in between, hence reducing the poly spacing rule requirement. I think TSMC will use this layer to chop off poly gates.
 
I meant documents, other than DFM DRM..Documents used to give rough and simple description,
 

jeevan.life said:
Cut poly is used to reduce cell spacing. Instead of following the regular DRC rules, by using cut poly, you can have a single poly shared between two devices with cut poly inserted in between, hence reducing the poly spacing rule requirement. I think TSMC will use this layer to chop off poly gates.
Click to expand...

i got the concept you explained above, but still i have some doubts related to its usage

1. this layer is used in only standard cell layouts or can also be used in analog? or in analog we should follow min spacing between poly instead of going for CPO?

2. part under the CPO is not fabricated? or will it be chopped off after fabrication of poly?
 

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