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Can't show it in C@dence, sorry.
Use a test bench similar to this one:
Use a fixed Vdd and Vgs which suits your application, then run a DC sweep Ids analysis. With the ADE calculator, you can directly plot Ron = Vds/Ids vs. Ids (not possible with my simulator plot tool).
Hi, already suggested by erikl, you can also sweep the Drain-source voltage from 0 to VDD and connecting gate to highest potential, you can get ron resistance in the triode region.
I have attached the test bench view of candence. https://obrazki.elektroda.pl/9617413300_1349844483.jpg
I don't think it is meaningful if you plot ron vs. Vds (or vdd) : Dameash wants to see ron in deep triode region, i.e. at very low Vds. I think it's better to sweep Ids and plot Vds (resp. Ron) vs. Ids.
Yes erikl, you are right, but giving ideal current sweep may lead the output voltage to increase infinitely. So off course one another way will be sweep the Vds.
Thank you all for your replies. It was useful in trying to understand the concept.
Varunkant : can you explain how to make ron as a output variable in cadence?
Also i want to know if we can plot Ron in deep triode for Vgs sweep. How should the graph look like and also how to do this.
This is how i am trying, please let me know if it is right. I am doing a dc analysis on nmos first. then i am trying to do parametric analysis on Vgs keeping Vdd constant and small so that the device operates in deep triode.
In this way when i try to get the Ron, it has negative values. This proves that i am going wrong at some point.
damesh! if you use cadence then use calculator option and define the ron by Vds/ids.
If you plot this , you can get what you say "output ron veriable".
Off course Vgs can be swept as well. If you know the Vds voltage or nature you can modify the test bench(either give vds fixed voltage or use the active or passive load).
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