Assura - LVS - std cell design

Hello,

I got another question which I want to ask. I hope you can help me. The situation in short notes:

* Chip (with IO cells) finished and Streamout as GDSII and Verilog
* GDSII Xstream In to Virtuoso
* Assura streamed in Layout vs. Verilog Netlist (+ the Spice Netlists of the std. cells)

Everthing is working fine, but I get lots of Missmatches. Most of them are VSS and VDDD Ports of all std cells in the Layout. I read some in www/forums and got the Information to manual create global nets in the Layout. I tried this with "create pin" and "create label". But the results are the same. So my question is, how to solve these errors? I don't think that they are real or in more detail:

* Have I to create such global nets in virtuoso? Why? Because the Verilog does not have such definitions for VDD, VSS.
* Where I have to create them? On the internel power rings or at the pads of the IO power cells at the chip boundary.
* How I have to create them?
* Are other solutions possible?

Because I'm a digital designer guy, I have not much experience with virtuoso. Therefore, it would be create if you can explain me in detail what to do. Thank you so much.

Greetings from Germany,

Marc

PS: Import of the Verilog to a a Virtuoso Schematic does not work due cadence internal memory violation. Therefore the only way is to do this directly in LVS with verilog and spice netlists.

Check Assura Physical Verification Developers Guide.
Verilog does not explicitly support global signals, but it does support the constant signals of tie0 and tie1. Assura treats them as global nets.

For LVS to connect tie0 and tie1 to your real ground and power nets, you should add the
joinNets command to the avCompareRules section of your RSF, as illustrated in this

example.
joinNets( root "gnd!" "tie0" )
joinNets( root "vdd!" "tie1" )
-=-=-=-=-=-=-=-=

Regarding Layout of STdCells - they must be having some VDD VSS in the GDS - make sure Assura Extract rule is reading them - through textToPin( layer ...) etc..