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pwm generation for smps...?

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s.manikandan

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pwm generating.

consider if,

error amplifier reference voltage = 2.5V (non-inverting input)
output feedback voltage to error amplifier = 1.5V ( inverting terminal)
now the error amplifier output is = 2.5 -1.5 = 1V

Now,Ramp signal amplitude = 5V
error amplitude is = 1 v( as above)

now the PWM will increase Ton period to match the vref voltage... My doubt is, when error is ZERO, how the ramp signal and error signal comparison takes place. what will be the output... because the comparison takes place only if error is generated... otherwise.....?
 

Hello

In general, PWM ICs have internal dead-time generation, which is what the minimum allowed DC reference to give the minimum duty-cycle is called. These things should be specified within their data-sheets. If you have built your own PWM generator with discrete components, then you should introduce a minimum DC level to forbid the comparator outputting continuously high-state that would possibly permanently damage the switch. Do note, though, that some ICs allow 0% duty-cycle, but that is also specified in their data-sheets and if it is so it's because there may be some special requirements to do so.

At any rate, if your application can't handle less than a minimum duty-cycle, then you should provide it.


Vlad
 
bubulescu said:
Hello

In general, PWM ICs have internal dead-time generation, which is what the minimum allowed DC reference to give the minimum duty-cycle is called. These things should be specified within their data-sheets. If you have built your own PWM generator with discrete components, then you should introduce a minimum DC level to forbid the comparator outputting continuously high-state that would possibly permanently damage the switch. Do note, though, that some ICs allow 0% duty-cycle, but that is also specified in their data-sheets and if it is so it's because there may be some special requirements to do so.

At any rate, if your application can't handle less than a minimum duty-cycle, then you should provide it.


Vlad
Click to expand...


K. But there is no dead time generation in many general PWM controller IC's like sg3525 & some general purpose ic's. There, it specifies minimum duty cycle 0% ,maximum 49%.

Then how its working in zero error value.because every power supply, the pwm controller should generate theoretically calculated PWM duty cycle.. but how it happens.....? ... share with me as much you know.....
 

0% dead-time means zero output value after the comparator, 100% dead-time means continuous on-state. Between these two, which one do you think is to be avoided? Therefore, 0% means the source stops switching, which is the cheapest, most simple of the protections. What I said about the minimum level refers to the 100%, a bad choice of words, my apologies if it confused you, and as for the handling part, that's just as I said: if it can't handle, provide it. So, SG3525 allowing 0% dead-time isn't bad, it's actually welcome, but note the maximum 49% (dual output) which prevents the outputs from being damaged.

Vlad
 
s.manikandan said:
pwm generating.

now the PWM will increase Ton period to match the vref voltage... My doubt is, when error is ZERO, how the ramp signal and error signal comparison takes place. what will be the output... because the comparison takes place only if error is generated... otherwise.....?
Click to expand...

HI ,
The comparison will take place the pulse width will be minimal sometimes no pulse at all. Hope you found this usefull if so click the helped me button below
regards ani
 
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