[SOLVED] Problems in logical sinthesis on Design Vision.

read_lib D_CELLS_MOS_typ_3_3V_25C.db
Reading '/home//filtros/slogica/techlib/xh035/liberty/D_CELL/MOS/D_CELLS_MOS_typ_3_3V_25C.db' ...
Error: /home/joaonizer/filtros/slogica/techlib/xh035/liberty/D_CELL/MOS/D_CELLS_MOS_typ_3_3V_25C.db: Lexical Error on line 1 at or near '
'. (SCAN-4)
Error: A syntax error is found before the library or phys_library group.
	The compilation is terminated. (LBDB-153)
0

set search_path {"."  "../../techlib/xh035/liberty/D_CELL/MOS"}
set symbol_library { D_CELLS.sdb  }
set target_library { D_CELLS_MOS_typ_3_3V_25C.db }
set link_library { D_CELLS_MOS_typ_3_3V_25C.db dw_foundation.sldb}
set synthetic_library { dw_foundation.sldb }
set verilogout_equation "false"
set verilogout_no_tri "true"
set write_name_nets_same_as_ports "true"
set verilogout_single_bit "false"
set hdlout_internal_busses "true"
set bus_inference_style "\%s\[\%d\]"
set sdfout_no_edge "true"
echo "Please use: set_fix_multiple_port_nets -all"
read_lib D_CELLS_MOS_typ_3_3V_25C.db
set hdlin_auto_save_templates "true"
define_design_lib work -path ./work

Warning: Unable to resolve reference 'mult_TipoII_2Bits_1' in 'operando2_Multn16_m2'. (LINK-5)
Warning: Unable to resolve reference 'mult_TipoII_2Bits_0' in 'operando2_Multn16_m2'. (LINK-5)
Warning: Changed instance name U11 to U11_inst in module Fil_30_LP2. Please use the change_names command to make the correct changes before invoking the verilog writer.   (VO-1)
[\CODE]

There are more than 200 warnings like that, so i'd like to know if i need to worry about this, or how to correct them. I've been loking on my SV code and everything is Ok about the instantiations (in my point of view and knowledge). In the functional verification everything seemed to work.

[CODE]
\\Instantiation of MTII in operando 2:
mult_TipoII_2Bits MM1 (A1, A0, B3, B2, RP13, RP12, RP11, RP10);
mult_TipoII_2Bits MM2 (A1, A0, B5, B4, RP23, RP22, RP21, RP20);

\\Begining of mult_TipoII_2Bits module:
module mult_TipoII_2Bits(A1, A0, B1, B0, S3, S2, S1, S0);
input logic A1, A0, B1, B0; 
output logic S3, S2, S1, S0;

set link_library "* D_CELLS_MOS_typ_3_3V_25C.db dw_foundation.sldb"