PWM burst output PIC18F

Hi, I want to use the ECCP PWM peripheral on a PIC18F in half-bridge mode to produce an ouptu signal of 40kHz, 50% duty cycle, and I want to be able to switch this on and off so that I can produce bursts of a 40kHz carrier, with a fixed duration - i.e. have a function with "burst width" or "number of cycles" as a parameter to control it.

Is there an efficient way to 'burst' the PWM on and off, without having to disable/enable the PWM module or associated timer, and without having to reset all of the control register settings for the 40kHz wave. The application is time-critical, so the duration between the start of the burst and the end of the burst needs to be known/controlled accurately.

I believe I have the PWM and TMR2 modules initialised correctly, but I'm worried that just enabling/disabling the PWM for the burst would mean having to re-initialise the modules, and I wouldn't know the time.

Hi,

All you need do is set up the PWM, with CCRP1/2 set to 0% duty .
When you want to send your signal then load CCRP1/2 with dec 128.
When you have sent the signal for the requried time then set CCRP1/2 back to 0

To change CCRP1/2 takes just the odd instruction so you are looking at a couple of nano seconds which is hardly going to affect any 40K signal.

The pictures show the idea on a sim scope, signals just what I had running about 1Khz I think.

Thanks, it seems like a good solution, but the time precision needs to be 3us - that is the time difference between the PWM function being called, and an actual output change on the PWM pins needs to be accurate to less than 3us (T +/- 1.5us, where T is constant).

My worry with this method is that since my 40kHz square wave has a pulse width of 12.5us (50% duty cycle), then when I call the function, the output on the pwm pins could change immediately depending on the phase of the pwm/tmr2 clock, or it could change at close to 12.5us after, since the PWM/tmr2 clock is at a different frequency to Fosc. So this could be an error of up to 12.5us instead of 3us. Do you think this could be a problem?

edit: I'm thinking about bit-banging the PWM in software using I/O pins so I could have something like:

nabla101 said:

Thanks, it seems like a good solution, but the time precision needs to be 3us - that is the time difference between the PWM function being called, and an actual output change on the PWM pins needs to be accurate to less than 3us (T +/- 1.5us, where T is constant).

My worry with this method is that since my 40kHz square wave has a pulse width of 12.5us (50% duty cycle), then when I call the function, the output on the pwm pins could change immediately depending on the phase of the pwm/tmr2 clock, or it could change at close to 12.5us after, since the PWM/tmr2 clock is at a different frequency to Fosc. So this could be an error of up to 12.5us instead of 3us. Do you think this could be a problem?

Click to expand...

Hi,

You say you want to use two ECCP outputs in half bridge mode, but why , if as you now say that could introduce that start up error.

You do not say what 18F chip you are using , but I expect you could use the standard CCP modules and run both CCP1 and CCP2 together, so you get identical signals, as I showed in those pictures.

Though I mentioned it takes about 3 us ( not ns as I saideariler ! ) thats when a 4 Mhz oscillator is used, many 18Fs can go a lot higher so your turn on time will be a lot less.

However you do not mention what is receiving the 40K signal for 3 us to be so critical ?
Also wonder about the signals On time, assume that must be equally critical that is timed to the us ?

Hi,

I'm not saying the half-bridge mode would cause the error, but rather the starting phase of the pwm output when the duty cycle is written, which would exist even for a single PWM output (At least that is what I think would happen, since the pwm clock is at a different frequency to Fosc, and writing a new duty cycle to the pwm register does not adjust the pwm clock phase to generate an output change immediately after the instruction - or does it??). I'm using 18F66k80, at Fosc = 64MHz, so an instruction cycle rate of 16MHz, or Tosc*4 = 62.5ns, which is an acceptable error for all timings in the output signal (Period, pulse width, start-up time, and delay between outputs going high to avoid shoot-through current in the bridge) - this is why I'm now thinking of bit banging (edited my post above^^).

nabla101 said:

Hi,

I'm not saying the half-bridge mode would cause the error, but rather the starting phase of the pwm output when the duty cycle is written, which would exist even for a single PWM output (At least that is what I think would happen, since the pwm clock is at a different frequency to Fosc, and writing a new duty cycle to the pwm register does not adjust the pwm clock phase to generate an output change immediately after the instruction - or does it??). I'm using 18F66k80, at Fosc = 64MHz, so an instruction cycle rate of 16MHz, or Tosc*4 = 62.5ns, which is an acceptable error for all timings in the output signal (Period, pulse width, start-up time, and delay between outputs going high to avoid shoot-through current in the bridge) - this is why I'm now thinking of bit banging (edited my post above^^).

Click to expand...

Hi,

Afraid I cannot answer your points there, as its not something I have tried and tested myself.

Perhaps if you say what your bridge is made of and what motor its driving then others who have experience of them will come in and help you.

My thoughts would be that it will not cause a problem otherwise it kind of implies no one can use the Pics half or full bridge pwm without fear of blowing things ..