tariq786
Advanced Member level 2
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Some verification people perform mixed RTL + Gate-level simulation for various reasons including
1) when full RTL design is not synthesized yet . That is Only some part of RTL is synthesized and the synthesized gate-level portion is simulated with the remaining RTL.
2) validating ECO (engineering change order) where one gate-level block is simulated with the rest of the RTL
3) speed up compared to pure gate-level simulation.
The question is
Doing mixed RTL+Gate-level simulation does get a speedup over pure gate-level simulation but does n't this hide bugs due to X pessimism or X optimism?
For example, if pure gate-level simulation is done, a certain net/register would be X. By mixing RTL and gate-level simulation, it is possible that you would hide the X bug.
How to address the kinds of issues related to X pessimism or optimism in mixed RTL + gate-level simulation.
How to learn from your point of view.
THanks
Kind Regards,
1) when full RTL design is not synthesized yet . That is Only some part of RTL is synthesized and the synthesized gate-level portion is simulated with the remaining RTL.
2) validating ECO (engineering change order) where one gate-level block is simulated with the rest of the RTL
3) speed up compared to pure gate-level simulation.
The question is
Doing mixed RTL+Gate-level simulation does get a speedup over pure gate-level simulation but does n't this hide bugs due to X pessimism or X optimism?
For example, if pure gate-level simulation is done, a certain net/register would be X. By mixing RTL and gate-level simulation, it is possible that you would hide the X bug.
How to address the kinds of issues related to X pessimism or optimism in mixed RTL + gate-level simulation.
How to learn from your point of view.
THanks
Kind Regards,