mixed RTL and Gate-level simulation

Some verification people perform mixed RTL + Gate-level simulation for various reasons including

1) when full RTL design is not synthesized yet . That is Only some part of RTL is synthesized and the synthesized gate-level portion is simulated with the remaining RTL.
2) validating ECO (engineering change order) where one gate-level block is simulated with the rest of the RTL
3) speed up compared to pure gate-level simulation.

The question is

Doing mixed RTL+Gate-level simulation does get a speedup over pure gate-level simulation but does n't this hide bugs due to X pessimism or X optimism?

For example, if pure gate-level simulation is done, a certain net/register would be X. By mixing RTL and gate-level simulation, it is possible that you would hide the X bug.


How to address the kinds of issues related to X pessimism or optimism in mixed RTL + gate-level simulation.


How to learn from your point of view.

THanks

Kind Regards,

If you want to catch x propagation kind of issues at RTL level before you move to GLS you have to do coding in such manner. For example if we know a clock can go to x then in rtl we have to capture such a way that the ouput corrupts if clock is x

Your question is very similar to the question "what shall I do to make sure that what I simulate in RTL is exactly what I got from Gate-level simulation ?" . And the answer is not so easy but I can list some of things in my mind that can help in partially answering this question :
1) You have to follow RTL coding guidelines . These guidelines wasn't made for just annoying RTL designers but rather to make sure you don't got fake results in RTL simulations
2) have a complete sensitivity lists for computational blocks
3) make sure that you don't have timing issue using Static-timing Analysis
4) make sure you are handling all CTS "clock-domain-crossings" in the right way.
5) if you are using multi-power domains in your design you have to take care alot for all signals crossing from one power-domain to another , by adding the proper isolation cells / retention cells and make sure that you are controlling these isolation/retention cells in the right way
6) Avoid the usage of computational loops completely
7) as much as you can don't use non-standard logic styles (e.g. asynchronous logic)

There must be other things that I don't recall now.