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speedup of more than 2x in gate-level simulation

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tariq786

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Hi,

I am trying to do functional gate-level simulation (zero-delay) which means withOUT timing.

Please see the attached figure

When i run the gate-level simulation of the original design, it takes 160 minutes of wall clock time.

When i partition the design into 2 partitions and do mixed RTL and gate-level simulation, it takes 64 minutes and 74 minutes

So the speedup is 160 / max(64,74) = 2.18


How can this speedup of more than 2x be justified? I have made sure that every thing is correct and there is no optimization or any thing being done by the simulator.

Your input and comments will help me understand better.

Please see the attached figure

Thanks and kind regards,
 

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  • traditionalGL_vs_parallelGL.jpg
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That is very normal.
The gate-level netlist usually is much more complicated than RTL with respect to both the number of variables/nodes ( which affect memory) and number of operations (which affect processing) . The second point you might be missing is that simulation time is not just linear function of the circuit complexity, which means that when you double the complexity of the circuit you want to simulate, the simulation time may increase three times or four times or even more depending on many factors. Some of the factors that affects the simulation time is the amount of nodes you are storing their waveforms, the amount of text messages generated by the simulation, whether or not your PC needs to make memory swap .
 
Fahmy dude,

Thanks for the explanation. Is there any literature or paper or document supporting your answer? I would really appreciate that.

Kind Regards,
tariq786
 

Hi tariq786,
Actually this was based upon my experience only , maybe there are some literature about that but I don't know any.

Regards,
Fahmy
 
There are scores of papers available from IEEE conferences. In particular, check the Design Automation Conference and search for "event driven simulation performance"
 
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