tariq786
Advanced Member level 2
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Hi,
I am trying to do functional gate-level simulation (zero-delay) which means withOUT timing.
Please see the attached figure
When i run the gate-level simulation of the original design, it takes 160 minutes of wall clock time.
When i partition the design into 2 partitions and do mixed RTL and gate-level simulation, it takes 64 minutes and 74 minutes
So the speedup is 160 / max(64,74) = 2.18
How can this speedup of more than 2x be justified? I have made sure that every thing is correct and there is no optimization or any thing being done by the simulator.
Your input and comments will help me understand better.
Please see the attached figure
Thanks and kind regards,
I am trying to do functional gate-level simulation (zero-delay) which means withOUT timing.
Please see the attached figure
When i run the gate-level simulation of the original design, it takes 160 minutes of wall clock time.
When i partition the design into 2 partitions and do mixed RTL and gate-level simulation, it takes 64 minutes and 74 minutes
So the speedup is 160 / max(64,74) = 2.18
How can this speedup of more than 2x be justified? I have made sure that every thing is correct and there is no optimization or any thing being done by the simulator.
Your input and comments will help me understand better.
Please see the attached figure
Thanks and kind regards,