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From RTL perspective I do not see any differences. But from implementation point of view you need to think in FPGA whether resources are present or not.
When you do ASIC design, you should ensure that you design is testable using DFT methodologies like SCAN BIST, MBIST and at speed test control if needed. This means that all flops reset and clock should be drivable with test reset and test clock during test mode. Normally we would be adding a test mux to mux between the test clock and functional clock before the clock is fed to a flop (or number of flops). This is not required in FPGA design.
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