[SOLVED] Feedback loops in synchronous processes - VHDL schematics

Hi,

I've seen that feeding back an output to a block requires a delay element between the output and the input linked to it; is the delay element necessary for clocked blocks too or only for combinatorial blocks?

Thanks guys

What are you refering to when you say "delay elements"? Combinatorial logic should never feedback on itself.

TrickyDicky said:

What are you refering to when you say "delay elements"? Combinatorial logic should never feedback on itself.

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let's say i have to compute a+b, where b is the output of the block that performs the sum. my point is: if the adder has 3 ports (a,b, clock), can I just feed b back as input without a one-clock delay?

or do I need a register that holds for one clock cycle the output of the adder before feeding it back?

if the adder has 3 ports (a,b, clock), can I just feed b back as input without a one-clock delay?

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An adder as such doesn't utilize a clock. If the "adder" has a clock input it's most likely an adder with in- or output register. Then the output can be of course feed back to the input, forming an accumulator respectively integrator.

FvM said:

An adder as such doesn't utilize a clock. If the "adder" has a clock input it's most likely an adder with in- or output register. Then the output can be of course feed back to the input, forming an accumulator respectively integrator.

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and there is no need to delay the input I feed back to it, right?

there is no need, but it wont work as you expect. Use a clock and make life simple.

TrickyDicky said:

there is no need, but it wont work as you expect. Use a clock and make life simple.

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I will. Actually, maybe I am already : the "adder" has two inputs besides the clock; the output is fed back as one of the inputs without being delayed. Is this what you suggest?

It shouldn't be too difficult to find out what the clock actually does. Either it feeds registers or it's simply unconnected.

There are two kinds of logic - combinational and synchronous.

The idea is to use combinational logic to do something, like add from a few sets of inputs. The result is available as soon as possible, with some gate delays. If there is too much going on, the differences in the delays through different paths will make your life hell. So we keep it as simple as possible, and register the results on a clock transition. That's synchronous logic.

It is really an organizational issue. With a small combinational circuit, we can guarantee (or at least measure) the worst-case delays. Now as long as the clock cycle is a little more than the worst case, our circuit is guaranteed to work.

So in your case, add, whatever. Register the result. Now you can connect the registered result to one of the inputs. Any other way of thinking (feedback loops or whatever) is just confusing to everyone.

stacksmith said:

So in your case, add, whatever. Register the result. Now you can connect the registered result to one of the inputs. Any other way of thinking (feedback loops or whatever) is just confusing to everyone.

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That's what I did, as anticipated; apparently it's working. Thank you.

Thank you all guys for answering, it helped.