Post layout design adjustement without editing layout

Hi,

I am doing post layout simulations in cadence spectre using generated parasitic file from calibre PEX tool. Simulation results show different results than compared with pre-layout simulations. Therefore, i need to tune the layout to make the circuit working with parasitics. Previously, i used to edit the layout, generate the parasitic extraction file once again and re-run the post-layout simulations for tuning the layout. However, this process takes a long time as layout editing is quite time consuming. Is there anyway that i can tune the layout by editing the extracted netlist and later on when my design is final i can edit the layout in final run. In this way i will not have to edit the layout many times..

Looking forward for your suggestions.

Of course you can edit the extracted netlist, but this is also tedious and troublesome, unless you know exactly what and where you have to edit. If so, this method may be helpful. But the problem still is to match the layout to your edited netlist finally.

I've successfully done this for better matching of transistor and cap arrays (including their wiring) for a high-resolution ADC.

From Cadence analogLib, you have pres, pind and pcap component. You can include them in schematic (they are ignored during the LVS) and tune parasitic value of these component.