Capacitor without a current limiting resistor

Hi,

Sometimes a small capacitor is placed in a circuit without a current limiting resistor. An example of this is the capacitor that is placed at the input of the circuit for ESD protection. In this case no current limiting resistor is placed. Theoretically when the input goes up, infinite current will flow through the capacitor. Practically the short duration of the current will not cause any damage and the current is limited by the output impedance of the source an the wires/tracks on the PCB.

My question is: how do i calculate the maximum value of the capacitor that does not need a current limiting resistor? Is this specified in the datasheet? Or is it something you just learn by experience?

Thank you in advance.

Theoretically when the input goes up, infinite current will flow through the capacitor.

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That's inaacurate!
A very important value of a capacitor is the ESR.
It plays the most important role in answering your question

I doubt that capacitors are a good means for ESD protection. ESD strength is mainly a matter of absorbed energy, a capacitor doesn't absorb energy, just store and release it.
Reducing ESD voltage to safe levels requires unrealistic large capacitors.

Current limiting will be mostly provided by source resistance, I presume. In so far the question is rather hypothetical.

The ESD circuits that provides the current have its own internal impedance (both resistance and inductance). This limits the capacitor inrush current.

As FvM says, you need rather large capacitance to be effective as ESD protection. You should think of several 100nF. Note that capacitors have limited peak current handling capability. Large ESD transients may damage a ceramic capacitor.

Inrush current can be a problem in connecting circuits to a supply that already supplies current to other circuits. As the supply has limited current capability, the voltage may drop for a short time just after connecting the new circuit (with capacitance). If this is not taken into account during the design of "hot-swap" application, one may see resets and other problems....

Regarding maximum peak current in ceramic capacitors, this isn't specified mostly. You may try to locate "DC, AC and Pulse Load of Multilayer Ceramic Capacitors" from yageo / phicom (former Philips Components). This document describes the effect of ESD pulses on MLCCs.

Faddei said:

Hi,
...... the capacitor that is placed at the input of the circuit for ESD protection....

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Are you sure the cap is there for ESD protection ? Or is that an assumption you are making.
All else will depend on this

rohitkhanna said:

Are you sure the cap is there for ESD protection ? Or is that an assumption you are making.
All else will depend on this

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It is an assumption indeed. But i guess there are situations where a capacitor is placed without a current limiting resistor (for filtering maybe) and my question is how to determine if the capacitor will survive this and if it will not load the source too much.

As WimRFP clarified, there's a risk of damaging MLCCs by ESD currents. A series resistor won't help against it. In normal operation, there's however little chance to provide current levels dangerous to the capacitors, except in power electronics applications.