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How to find Flip Flops & Latches & Buffers in RTL Compiler

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lannister7

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After synthesizing the netlist - i want to use the find command to find the flip flops in design, buffers , latches etc in the design. How to get this information in RTL compiler ??
 

Hai lannister,


We can get this by commands itlself which compiler u r using??? Also u can easily pick in help document


IF u r not inside tool and u want to find in netlist then u can write a script on your own...ITs simple......
 

foreach_in_collection c [get_cells -hierarchical * -filter "@ref_name=~latch*"] {
set cn [get_attribute [get_cells $c] full_name]
echo $cn
}
 

here you go..
rc:/> filter flop true [find / -inst *]
rc:/> filter latch true [find / -inst *]
rc:/> report gates (this will give you a count of buffer and inverters in the design)

For other sequential elements you can also try "report sequential"
 
Thanks Guys !

That Helps !! I also wanted to find the Buffers in the Design. I'm using RTL Compiler RC 11.0 , After synthesis, (incremental) - i need to find the buffers n remove them - is there any such command for that??
 

May i ask you to pls elaborate why do you wish to do so? This will destroy your design timing + fanout opto also if you have done.

I can suggest an automated way - would be to mark all buffers as set_dont_use and perform an incremental optimization - but this may replace all bufferes with inverter pairs
 

remove_assigns_without_optimization

Controls the aspects of the replacement of assign statements in the design with buffers or
inverters without performing incremental optimization.

all des seqs

The above command also list flops:cool:
 

The reason is , after synthesis i see about a 7000+ buffers in design, which is a significant area number/power number, so i was wondering what is the optimized area for the design w/o buffering.

I'm not trying to make it match any timing for now, but i'm looking at options for reduction of area/power.

So, if i write out the netlist - with buffers in them, now can i use an edit netlist command to make changes to this?



englishdogg said:
May i ask you to pls elaborate why do you wish to do so? This will destroy your design timing + fanout opto also if you have done.

I can suggest an automated way - would be to mark all buffers as set_dont_use and perform an incremental optimization - but this may replace all bufferes with inverter pairs
Click to expand...
 

@vijayR15

The command you suggest "remove_assigns_without_optimization" will add buffers to remove assign statements - the idea / request here is to remove usage of buffers.

@lannister7

This exercise is of no use - even if you say save area by 20% you will finally have to add buffers for timing or HFO.
That being said - i dont have a ready utilty to help you here but this should be the flow of the utility
1. find all buffers in the design
2. find driver and load for each buffer and save it in a var
<here the load can be more than one as well>
3. disconnect both the connections
4. connect the driver to the first load (use lindex for the var)
5. rm the buffer instance

Hope this helps..
 

@englishdogg

ya but the above command will reduce the usage of buffers for replacing assign statement.. Replacing assign with buffer for top module is enough.. right..
Even if u change all buffers with inverters we cant see much difference in the area..
We cant completely remove all buffers u need to takecare of feedthrouh paths also...
 

no... i believe i was not quite verbose in my earlier append
On usage of this command tool will add buffers to remove assigns; the assigns whatever may be the count will be in the netlist and that may still be required to be removed.
Also this will apply if in the design assign removal is performed

I am not sure i understand your concern on assign removal at top level - you can perform assign removal on a specific hierachy but my understanding says it has to be done across
 

@englishdogg,
fine, even if u replace all assign statements across... u could still see some assign statement in postlayout netlist...

@lannister7
May be ur design needs buffers to satisfy timing.. I am thinking that rc tool is adding buffers to optimize timing... we should not vary frequency but just for trial case reduce the frequency little and check whether it meets within your area..
 

i agree with timing critical nets. but this design was meeting timing and had a positive slack and had a huge area. i have a 570 ns positive slack so i thought removing buffers will help optimize the design.


vijayR15 said:
@englishdogg

ya but the above command will reduce the usage of buffers for replacing assign statement.. Replacing assign with buffer for top module is enough.. right..
Even if u change all buffers with inverters we cant see much difference in the area..
We cant completely remove all buffers u need to takecare of feedthrouh paths also...
Click to expand...
 

oh k fine thats good lannister..

May ur synthesis scripts may have some additional things..
Then In ur flow just try with three things in read_hdl, elaborate and synthesis synthesis.. May help ... sorry if not..

read_hdl
elaborate
synthesize -to_mapped -eff $MAP_EFF -no_incr $TOP_MODULE
 

@lannister7
depends on the clock frequency and max fanout permitted - but without buffers your timing may not close or even may fail for drc violations
 

An alternative ECO way, in perl format by using Netlist ECO tool Gates On the Fly
# remove_buf.pl
my @bufs = get_cells("-type", "buf", "-hier");
foreach my $buf (@bufs){
my @loads = get_conns("-load", "-pin", "$buf/Y"); # To simply, assume you know the buf has A/Y as pins
foreach my $load (@loads){
change_pin($load, "$buf/A");
}
}

And use this command to run
gof -lib your_lib.lib the_netlist -run remove_buf.pl

Goto www.nandigits.com to get "Gates On the Fly".

Let me know if you need licenses.
 

@nandy

perfoming the above - will it confirm that timing is met or is same before and after this change
 

englishdogg said:
@nandy

perfoming the above - will it confirm that timing is met or is same before and after this change
Click to expand...

Timing has to rerun. The command lines only remove buffers. User has to make sure there is no timing issue.
 

so if i understand well... this ECO is not timing aware... just plain netlist editing
 

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