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[SOLVED] Help needed in Interview Question!!

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sakthikumaran87

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What is the max freq of the circuit with clk to Q period of 2ns, comb delay of 3ns, setup of 1ns and a skew of -1 ??
 

2ns + 3ns + 1ns +1ns = 7ns

this is the min period, 1000/7 = max freq, unit(M)
 

You can use this formula--

Max Clock Freq = 1/ Max (Reg2reg, Clk2Out, Pin2Pin)

you can also refer the following link Problem2-

example of Setup and Hold time

let meknow if this helps u
 

can u pl explain why 7ns?? Even i gave the same answer and the interviewer accepted it. but today i came through an equation:

Tcyc ≥ TCQmax + TPmax + Tsetup+ Tskew

which contradicts this result. pl guide.
 

Tcq+Tcombi<=Tclock period-Tsetup-tskew
2ns+3ns<=Tclock period-1ns-1ns
2ns+3ns+1ns+1ns<=Tclock period
7ns<=Tclock period
Frequancy=1/Tclock Period
F=1/7*10-9
 

Tcq+Tcombi<=Tclock period-Tsetup-tskew
2ns+3ns<=Tclock period-1ns-1ns

Hei here i have given the tskew of -1, then wont it be -(-1) = 1??
 

Hi,

tcq + tcomb <= T + tskew - tsetup
T = clock period

So, for the above question, minimum time period is 7ns (its not 5ns).

For setup & max frequency calculation, skew is the added advantage.

regards,
Subhash C
 

Hi subhash

Only one thing i cant get is you have given T + tskew - tsetup but the equations in all the above posts points to T - tskew - tsetup. Can you pl explain why this contradiction occurs??
 


There are terms called, Negative Skew & Positive Skew, defined w.r.t the direction of the clock & input data coming to the design.
w.r.t above terms explanation for the above problem is given in the attached pdf file. Pl go through it.

regards,
Subhash C
 

Attachments

  • Negative Skew & Positive Skew.pdf
    226.3 KB · Views: 241
Thanks Subhash,

It is very clear now. I have no words to express my gratitude. Thank you once again.
 

Subash & SakthiKumaran,
If you guys are convinced that the frequency is 1/7, then feel free to go with it.

But to re-iterate my answer will always be 1/5 for your problem and I am pretty sure about it.

Best Regards
 

Hi All.

Pl share some interview questions and important concepts in STA and synthesis.
 


Based on my interview(s), I prepared this document.
pl find the attachment.
Hope it will help you all. At least it will show the path for STA learnings.
 

Attachments

  • STA_Questions.pdf
    20.3 KB · Views: 1,954
Negative skew play important role in this question.
Postive skew will beneficial for setup , where as negative skew beneficial for hold.
Negative skew means, the capture register is receiving the clock early compared to launch flop. Means, the insertion delay for the launch flop is more than capture flop. With negative skew, the effective clock period will reduce.

The above example will work at 1/5 .

Regards, Sam
 

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