Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Lint Checks are RTL checks which checks for unwanted latches and RHS != LHS Basically make sure there are no surprise after synthesis.
Training material you can search GOOGLE
Linting is a RTL Verification tool that checks the quality of the RTL code and find out any violation wrt to certain policies dictated by a group of companies. It will raise for almost all sort of errors like inference of latch as mentioned in earlier post to presence of logic in the top level file of the RTL. It is the responsibility of the designer to go through each error and find out whether it is really an error or to waive it off.
Coming to your second Q: No seperate scripting is required other to run the tool. Alternatively GUI mode is also available.
Verilog Code is verified through Lint check. Now a days gate level description is also verified through lint sometimes but i am not sure whether the SPYGLASS tool has the capability to check it. In Lint we have a seperate flow called CDC methodology which will highlight all CDC based errors.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
