Bulk Biasing , 0.18um Technology

0.18um technology

Hai Guys:

Is bulk biasing supported in 0.18um CMOS technology, as shown in the attached Figure, where RB1and RB2 are used for the bulk biasing purposes. Thanks in advance

Rgds

pmos bulk

With NMOS you cannot do it.
But You can use complementary schematic
with PMOS and you can do it.

transistor bulk biasing

Hi devrimaksin:

Thanks for your input, if you observe the paper:

Kwang-Jin Koh, Mun-Yang Park, et al.(2004). Subharmonically Pumped CMOS Frequency Conversion (Up and Down) Circuits for 2GHz WCDMA Direct-Conversion Transceiver. IEEE Journal of Solid-State Circuits, 39(6), 871-884.

there's and architecture proposing an In Phase Adder (IPA)utilizing NMOS in 0.18um CMOS technology with bulk biasing. Since the input to this stage is capacitively coupled from the previous stage, where the previous stage is an RC-CR phase shifter, a resistive ladder dc biasing at the gate of a IPA is not appropriate. Can you kindly suggest and alternative input dc biasing scheme despite the bulk biasing which is not supported by the process?. I would also appreciate if you can explain in detail on the PMOS bulk biasing which is supported by the process.

Rgds

nwell pwell bias

Hai ,

Is above mention circuit is implementated in Standrad cmos process ?

regards,

selvaraja

0.18um technology in layout

With NMOS you cannot do bulk biasing......

biasing

The process in that papar is 0.18um 1P6M, be careful, next part is the most interesting part, "triple well." I have no idea what "triple well" means, N-well, P-well, and what's next?

The reason people keep telling you that you can't do bulk biasing for NMOS is that there are few process providing P-well mask. Couple years ago, many processes got "twin-well," means N-well and P-well, you can do any bulk biasing on any particular transistor in that kind of process. However, manufacturing companies stopped making P-well to reduce cost, I think, because you don't need the P-well mask anymore.

So, nowaday, the manufacturing company make it more like P-well all chip wide unless you define some area as N-well. So the area outside N-wells can be treated as a big P-well and it has only one well contact and it has to be connected to the single voltage. That's why you can't bulk biasing the NMOS separetely because their bulk all connected together. You want bulk biasing the NMOS, bulk biasing all the NMOS transistors together.

Unless you can find a process that got P-well for NMOS, you can't do any bulk biasing on NMOS. I don't think the process used in that paper is TSMC 0.18um process.

0.18 um technology rules

Triple well means you have a deep Nwell.
Inside the deep N well, you can bias the bulk, which is P well.

deep n well mask manufacturing

if this is a pwell process, one can also use such a bulk bias structure.

it is up to the process.

0.18um nmos

The process is 1p6M TSMC 0.18U Mixed Mode process. Since I have used this process from MOSIS with a design kit, there are 2 transistors which has both bulk-source connected. So this has options of both n-well and p-well with p-well being in the deepNwell as indicated by the above post. So I guess this can be done in this circuit...

Venu

tsmc 0.18um process deep n-well

triple well process means nwell,Pwell and a deep Nwell.
In our Hitachi process, there are Nwell, Pwell and a so-named NISO which
acts as a third well for NMOS.

mosis tsmc 0.18um 1p6m

If the process is triple well, you can do it by deep nWell that can be isolated.