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[SOLVED] phase margin folded cascode

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paramis

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Hi all,
this is my result from simulation full differential folded cascode op-amp.
how can i measure phase margin ? from v(out+),v(out-) or v(out+,out-)?
I don't know why gain out+ or out- is less than (out+,out-)?
How can I cansel offset foldedcascode(input transistors are pmos)?
 

First of all in differential circuits, the differential output voltage gain is 6dB larger than each single ended output.

38 --> 44

If your circuit is fully differential, the phase-margin can be found from either by differential output or single ended ones. Both shoul give you the same phase margin.

You must not have offset in simulation. If you have, this means that you have systematic offset which is probabely due to imperfections in your CMFB design.
 
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