[STA] PVT vs OCV - are the same in terms of STA?

Hello All,

As for the PVT and OCV, do they mean the same things for the STA?

OCV - OnChip variations.
PVT - Process-Voltage-Temperature variations.

What do represent these phenomenas in STA? Are they represented just by the min/max libraries and min/max timing extractions in layout?

Thank you!

On chip variation is used to account PVT variation.

Could you elaborate that? What does it mean "On chip variation is used to account PVT variation"?

Go through this article.
https://asic-soc.blogspot.in/2008/03/process-variations-and-static-timing.html

Please go through the following link for more info.

**broken link removed**

Rgds,
Kumar

No these are not same.
PVT : Depending on Process Voltage Temperature delay of cell will change.
OCV: On Chip Variations same cell in across same PVT gives different delays.

PVT
Process voltage Temperature
If process increases then cell delay increases
If voltage increases then cell delay decreases
If temperature increases then cell delay increases

Due to the variations in PVT some timing derating factor is provided for on chip variation by the vendor to get pessimistic timing results

For setup lunch clock is made to come early and capture clock is made to come late
For Hold lunch clock is made to come late and capture clock is made to come early

For setup lunch clock is made to come early and capture clock is made to come late

Click to expand...

Should not it be vice verse - lunch clock is made to come late and capture clock is made to come early?

Yes,You are right....,it should be vice verse by mistake i wrote it like that...,

PVT is applicable for different wafers. OCV is applied on single wafer.

PVT ( process voltage Temperature)
a) process voltage and temperature vary die per die. This is handled by the min and max libraries. Slow process, low vdd and high temp is handled by max library. This is used for setup time analysis. while fast process, high vdd and low temp is handled by min library. This is used for hold time fixing. This is on die to die basis. this is more of a global phenomenon. This covers one die.

b) OCV (on chip variation) : now that you have die for example slow process, low temp and low vdd. There will differences within the die from one end to another. This is mainly due to device mismatch, process defects, and other physical effects. OCV is responsible for statistical variation within the die. In older technology , PVT analysis used to cover everything but in the newer technology doing a PVT design makes it too pessimistic so people try to optimize a little lax PVT analysis followed by OCV margning to reduce the pessimissim
.