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Gain-Bandwidth of a Multistage amplifier

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milvapp

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Hi all,

Theoretically speaking,lets say I have a multistage amplifier with 4 stages of amplifiers of the same topology.
Lets say that the first amplifier has a bandwidth Bwa which is bigger than the one of the second,so consider the following :
Bwa>Bwb>Bwc>Bwd
Does this above place some restrictions on the gain of each amplfier?
I mean,should all the stages have the same GBw?(which means that ga<gb<gc<gd)
Or can I arrange the gain of each stage the way I want?
Which strategy is wiser?

I am quite amateur to this so any help will be appreciated.
Thank you in advance
 

Hi,

When designing a multistage operational amplifier we care about the total gain requirement.This means that you arrange the gain of each of the inner amplifying stages according to your needs (i.e. if your design goal is a 3-stage operational amplifier with 85dB of total gain and you reach the 60dB from the 2 first stages,then you will try to design a final third stage with at least 25dB of gain).

Another useful tip is that we try to reach the biggest possible (in parallel with all the other specs we are given) unity gain frequency to the inner stages since poles,zeros and p-z doublets of next stages will reduce the total unity gain frequency requirement.PZ analysis of cadence virtuoso will help you watch and set the poles and zeros of your circuit and understand the whole work procedure of your circuit.

If you don't mind,are you designing a multistage amplifier as a training procedure to your university or to use it at a specific application.I am asking because i am doing something similar at the moment and maybe i can help you more or change opinions.

Regards,
Jimito13
 

jimito13 said:
Hi,

When designing a multistage operational amplifier we care about the total gain requirement.This means that you arrange the gain of each of the inner amplifying stages according to your needs (i.e. if your design goal is a 3-stage operational amplifier with 85dB of total gain and you reach the 60dB from the 2 first stages,then you will try to design a final third stage with at least 25dB of gain).

Another useful tip is that we try to reach the biggest possible (in parallel with all the other specs we are given) unity gain frequency to the inner stages since poles,zeros and p-z doublets of next stages will reduce the total unity gain frequency requirement.PZ analysis of cadence virtuoso will help you watch and set the poles and zeros of your circuit and understand the whole work procedure of your circuit.

If you don't mind,are you designing a multistage amplifier as a training procedure to your university or to use it at a specific application.I am asking because i am doing something similar at the moment and maybe i can help you more or change opinions.

Regards,
Jimito13
Click to expand...

Ciao ,I m a Italian student.....I have to find the working point of a 4-Stage OTA ....... But i dont understand how do i choose W an L to size the MOS ..... Can you help me, please x
 

Your question is very general :)
What OTA do you use?
The first step is to see what your specifications are and design the first stage according to it.
For example you can aim to get the highest BW at the first stage and the by adding stages you reduce BW and you increase gain.
The W,L depend on the transfer function of your OTA as from there you can see the poles and zeros.
But designing an 4-stage is not a easy procedure and you have to break it into pieces!
 

milvapp said:
Your question is very general :)
What OTA do you use?
The first step is to see what your specifications are and design the first stage according to it.
For example you can aim to get the highest BW at the first stage and the by adding stages you reduce BW and you increase gain.
The W,L depend on the transfer function of your OTA as from there you can see the poles and zeros.
But designing an 4-stage is not a easy procedure and you have to break it into pieces!
Click to expand...
thanks to answer me ;) it is this :
**broken link removed**
 

The paper gives you every detail you need :)
It gives you the gm in table I so there are 2 ways to find the W/L ratio.
First using the formula of gm and the current that flows each transistor you can evaluate the value of W/L .

The other way ,which is less precise is assuming that, that the transistors are in saturation and ytou suppose that Vgs-Vt is at least 0.2 V
And then you move one finding the W/L again.

I would recommend the first way because it will be better.If you think it's difficult try the second one but you will need more time to get the correct results.
You must understand the way the circuit works so that you understand what current (ideally flows) each transistor.The value for the current source at the start seems to be 1.4 mA.

So you can start with that :)
 

milvapp said:
The paper gives you every detail you need :)
It gives you the gm in table I so there are 2 ways to find the W/L ratio.
First using the formula of gm and the current that flows each transistor you can evaluate the value of W/L .

The other way ,which is less precise is assuming that, that the transistors are in saturation and ytou suppose that Vgs-Vt is at least 0.2 V
And then you move one finding the W/L again.

I would recommend the first way because it will be better.If you think it's difficult try the second one but you will need more time to get the correct results.
You must understand the way the circuit works so that you understand what current (ideally flows) each transistor.The value for the current source at the start seems to be 1.4 mA.

So you can start with that :)
Click to expand...
sorry,i hope to not disturbed you.......but waht is the formula gm ........i have not Kn Cox ......I am very confusion ;(
 

The formula of gm (considering that the transistors are in saturation ) is https://www.mhhe.com/engcs/electrical/neamen01/ch06.pdf
See pages 316-317 example 6.1 (sorry it is not easy to type the formula here ).
You will evaluate Kn (see 6.1 example again ) and the Cox should be known.It is a parameter of the technology you will use so it should be somewhere
in the description of your project :)
 

milvapp said:
The formula of gm (considering that the transistors are in saturation ) is https://www.mhhe.com/engcs/electrical/neamen01/ch06.pdf
See pages 316-317 example 6.1 (sorry it is not easy to type the formula here ).
You will evaluate Kn (see 6.1 example again ) and the Cox should be known.It is a parameter of the technology you will use so it should be somewhere
in the description of your project :)
Click to expand...

mmm......i don t know what is the library,because i write the comand an the cadence run alone........the prof. say me that i must use a typical value of W an L .......try and try .......but at this point i have many confusion........i look the example 6.1 .....it is banal,and i had made a lot probem of this in Electronic 1......them i made Electronic 2 from the another point of wiew,current mirror compensation miller ecc ecc.......
 

I think that by running DC operating point simulation in Cadence (see the manual ) you can
find all the information about your transistor.Cox.Cgd and so on..I told you to see example 6.1 because you wanted the equation for gm
 

milvapp said:
I think that by running DC operating point simulation in Cadence (see the manual ) you can
find all the information about your transistor.Cox.Cgd and so on..I told you to see example 6.1 because you wanted the equation for gm
Click to expand...

I have to do it ....... DC operating point .... I have two manuals on the instructions of a program and a layout .......

- - - Updated - - -

osvi said:
I have to do it ....... DC operating point .... I have two manuals on the instructions of a program and a layout .......
Click to expand...

you desappear......

- - - Updated - - -

osvi said:
I have to do it ....... DC operating point .... I have two manuals on the instructions of a program and a layout .......

- - - Updated - - -



you desappear......
Click to expand...

tanks really to your support.....grazieeeeeeeeeeee ;) but don t abandon me
 

ciao ;) have you been copy your schematic file in a dipositive usb to work in another pc?
 

Yes but before you do that make sure you set all privileges to 777 with chmod command
 
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