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Questions about standard cells & standard cells library

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R1kky

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Hi, Friends!

could you, please, help me with several questions regarding std cells & libraries.

1. what it (std cells libraries) can be (i.e. classification on vt,coarse-grain, fine-grain etc)

my suppose - vt could be high or low, also as mentioned coarse- or fine- grain, what else?


2. what track is?

my suppose - tracks mean routing resources, track is the path in which wires can pass through. One track is approximately the minimum spacing between metal1 and metal2 via in a technology node . Track is generally used as a unit to define the height of the std cell. For example, a 12 track cell will be taller than a 9 track cell, a 12 track std cell will be taller, that means more metal1 routing space is available within the cell, hence cells will be faster. where as in a 9 track cell, the cell will be compact, but speed is less compared to 12 track.


3. how many metal level using in std cells?

my suppose - 2 or 3 levels


4. what groups of std cells libraries consist? (for example, filler

my suppose - even don't know, as told there
A standard cell library is a collection of low-level logic functions such as AND, OR, INVERT, flip-flops, latches, and buffers. These cells are realized as fixed-height, variable-width full-custom cells. The key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimized full-custom layouts, which minimize delays and area.
A typical standard-cell library contains two main components:
Library Database - Consists of a number of views often including layout, schematic, symbol, abstract, and other logical or simulation views. From this, various information may be captured in a number of formats including the Cadence LEF format, and the Synopsys Milkyway format, which contain reduced information about the cell layouts, sufficient for automated "Place and Route" tools.
Timing Abstract - Generally in Liberty format, to provide functional definitions, timing, power, and noise information for each cell.
A standard-cell library may also contain the following additional components:
A full layout of the cells
Spice models of the cells
Verilog models or VHDL Vital models
Parasitic Extraction models
DRC rule decks
An example is a simple XOR logic gate, which can be formed from OR, INVERT and AND gates.
Click to expand...
so from that i can point only "logical elements group", what else?

thanks in advance.
 

R1kky said:
3. how many metal level using in std cells?

my suppose - 2 or 3 levels
Click to expand...

The number of metal layers depend on the foundry and the technology (45 nm, 65 nm). I have used 130 nm technology with 6 metal layers.

Thank you.
 
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    R1kky

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hairo said:
The number of metal layers depend on the foundry and the technology (45 nm, 65 nm). I have used 130 nm technology with 6 metal layers.

Thank you.
Click to expand...

thanks for answer, is it correct, that used number of levels of metal for whole SoC and for stnd cell libs is the same number or it differs?
 

R1kky said:
that used number of levels of metal for whole SoC and for stnd cell libs is the same number or it differs?
Click to expand...

I dont quite understand your question. In my design, I have a logic + memory block both using 130 nm and 6 metal layers in one die.

Thank you.
 

Usually, the std cell library contains only Metal1, sometimes it may contain M2. I never saw more than 2 metal layers in the std. cell library.

In addition to multi-Vt libs, exist multi-channel_length std cell libraries (also for leakage optimization).

Groups of cells (I do not know are there standards in naming of such groups):
Simple logic (nand, not, inv, buf, ...)
Complex logic (aoi, oai, 1-bit adder...)
Sequential (flip-flops, latches, scanFF)
Clock (clock buffers, clock inverters, clock-gating cells)
Misc (fillers, decap, tap, antenna diode, bus holder ...)
ECO (spare cells)
Power managetment (power switch, level-shifter, isolation, retention, always-on)
 
Usually, the std cell library contains only Metal1, sometimes it may contain M2. I never saw more than 2 metal layers in the std. cell library.
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Thanks sir. While doing a project on Std. cell we were allowed to use only M1 . But when we started layouts for higher drive strength gates , its became almost impossible to route , as M1 was overlapping. So how to come out of this problem and why don't we use M2 layer? Track size was 9.
 

But when we started layouts for higher drive strength gates , its became almost impossible to route , as M1 was overlapping.
Click to expand...
I've used std. cell library with x40 drive strength - and M1 was enough to draw such cells.

So how to come out of this problem and why don't we use M2 layer?
Click to expand...
Less metal layers in the std cells -> more metal layers for routing -> less chip area. The library, that contains M1+M2, used M2 only for power rails (reduce IR-drop and prevent EM issues).

The answer - if M1 is enough to draw all needed cells without area increasing of these cells - no reason to use additional metal layers inside cells.
 
Less metal layers in the std cells -> more metal layers for routing
Click to expand...
Sorry , my bad. But i didn't get this line. Sir can you elaborate this little more.
 

Metal2 usage does not depend on the drive strength of the cell. Complex cells like flop, scan flops and mux require metal2 (7 or 9 track require).

Metal2 usage blocks lot of routing resource when the particular cell is used in the design.
For example : U have used metal2 horizontally to connect two nets in "X" standard cell. And if routing direction of metal2 in the design is vertical.
If the "X" standard cell is used in the design, it blocks lot met2 routing resource.
 
How to choose the power rail width while designing a standard cell? I am designing a standard cell library in 180nm (cadence gpdk180). please help me in this regard..,
 

Re: Questions about standard cells & standard cells library

As discussed above, the MET2 is used only when MET1 routing is not possible.
Eg: IN High drive cells, MET1 is used as there is plenty of routing area.
Whereas in Flops,Latches and Scan Flops the MET2 usage might be present and it should be very minimal .

- - - Updated - - -

manu.srg said:
How to choose the power rail width while designing a standard cell? I am designing a standard cell library in 180nm (cadence gpdk180). please help me in this regard..,
Click to expand...

Hi Manu,

I have not worked on this.
But, based on the Understanding , Power Rail Width is measured by designing Inverters and running it in desired frequency , temperature and checking the voltage drop in VDD.

Based on the multiple iterations the power rail is chosen .
 

jeet_asic said:
Thanks sir. While doing a project on Std. cell we were allowed to use only M1 . But when we started layouts for higher drive strength gates , its became almost impossible to route , as M1 was overlapping. So how to come out of this problem and why don't we use M2 layer? Track size was 9.
Click to expand...

The reason behind using the lowest possible metal in designing the std.cell is that we do not create congestion for any other proceeding layer. Lets take an example : if i have a freedom of using all the metals available to design my std. cell, all the cells will have all the metals and once they are imported in the design i can't edit it any further. i will encounter problem while making the connections across the cells (one cell to another) also, another major reason is if i can utilize lower metals as much as possible then i would have more than sufficient area to do my routing in higher metals.

Now that the technology is developing things have come so far that we have most of the std.cell library across different technologies that have all their cells made using only metal 1.

in technology like 14nm/16nm we now have a Metal 0 that comes into existence.
 

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