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[SOLVED] hold violations due to clock gating

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anandmanivannan

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I have flops in the design whose clocks are gated by other flop outputs. Due to this, hold violations occur during ATPG.

What are the precautions that we should take when we use a clock that is gated by flip flop outputs.
 

Generate enable on negedge flop or use icg (latch plus AND gate)
 

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