Critical path delay with design compiler

for finding the critical path delay i have used the report_timing comand in my script and i get ths result but i don't know which data is critical path delay?
data arrival time?

thanks in advance

Startpoint: data_in[0] (input port clocked by vclk)
Endpoint: output[1] (output port clocked by vclk)
Path Group: vclk
Path Type: max

Point Incr Path
-----------------------------------------------------------
clock vclk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 f
data_in[0] (in) 0.00 0.00 f
U38/Y (NOR4XL) 0.31 0.31 r
U36/Y (NAND4XL) 0.15 0.46 f
U35/Y (NOR3XL) 0.24 0.71 r
U34/Y (NAND3XL) 0.28 0.99 f
U31/Y (AND2X1) 0.28 1.27 f
output[1] (out) 0.00 1.27 f
data arrival time 1.27

clock vclk (rise edge) 10.00 10.00
clock network delay (ideal) 0.00 10.00
output external delay -2.00 8.00

data arrival time 1.27